Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0e1e5c47 authored by Paul Zimmerman's avatar Paul Zimmerman Committed by Felipe Balbi
Browse files

usb: dwc3: add support for USB 2.0-only core configuration 



Newer DWC3 controllers can be built for USB 2.0-only mode, where
most of the USB 3.0 circuitry is left out. To support this mode,
the driver must limit the speed programmed into the DCFG register
to Hi-Speed or lower.

Reads and writes to the PIPECTL register are left as-is, since
they should be no-ops in USB 2.0-only mode. Calls to phy_init()
etc. for the USB3 phy are also left as-is, since the no-op USB3
phy should be used for USB 2.0-only mode controllers.

Signed-off-by: default avatarPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent 56700178

drivers/usb/dwc3/core.c

+7 −0
Original line number Original line Diff line number Diff line
@@ -386,6 +386,13 @@ static int dwc3_core_init(struct dwc3 *dwc) 
	}

	}

	dwc->revision = reg;

	dwc->revision = reg;





	/* Handle USB2.0-only core configuration */

	if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==

			DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {

		if (dwc->maximum_speed == USB_SPEED_SUPER)

			dwc->maximum_speed = USB_SPEED_HIGH;

	}



	/* issue device SoftReset too */

	/* issue device SoftReset too */

	timeout = jiffies + msecs_to_jiffies(500);

	timeout = jiffies + msecs_to_jiffies(500);

	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);

	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);

drivers/usb/dwc3/core.h

+13 −0
Original line number Original line Diff line number Diff line
@@ -191,6 +191,19 @@ 
#define DWC3_GHWPARAMS1_PWROPT(n)	((n) << 24)

#define DWC3_GHWPARAMS1_PWROPT(n)	((n) << 24)

#define DWC3_GHWPARAMS1_PWROPT_MASK	DWC3_GHWPARAMS1_PWROPT(3)

#define DWC3_GHWPARAMS1_PWROPT_MASK	DWC3_GHWPARAMS1_PWROPT(3)





/* Global HWPARAMS3 Register */

#define DWC3_GHWPARAMS3_SSPHY_IFC(n)		((n) & 3)

#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS		0

#define DWC3_GHWPARAMS3_SSPHY_IFC_ENA		1

#define DWC3_GHWPARAMS3_HSPHY_IFC(n)		(((n) & (3 << 2)) >> 2)

#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS		0

#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI		1

#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI		2

#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI	3

#define DWC3_GHWPARAMS3_FSPHY_IFC(n)		(((n) & (3 << 4)) >> 4)

#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS		0

#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA		1



/* Global HWPARAMS4 Register */

/* Global HWPARAMS4 Register */

#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)	(((n) & (0x0f << 13)) >> 13)

#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)	(((n) & (0x0f << 13)) >> 13)

#define DWC3_MAX_HIBER_SCRATCHBUFS		15

#define DWC3_MAX_HIBER_SCRATCHBUFS		15