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Commit 0e1c1c7a authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'samsung-dt-4.11' of... 

Merge tag 'samsung-dt-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Samsung DeviceTree update for v4.11:
1. Fixes for initial audio clocks configuration.
2. Enable sound on Odroid-X board.
3. Enable DMA for UART modules on Exynos5 SoCs.
4. Add CPU OPPs for Exynos4412 Prime (newer version of Exynos4412). This pulls
   necessary change in the clocks.
5. Remove Exynos4212. We do not have any mainline boards with it. This will
   simplify few bits later.

* tag 'samsung-dt-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux

:
  ARM: dts: exynos: remove Exynos4212 support (dead code)
  ARM: dts: exynos: Add CPU OPPs for Exynos4412 Prime
  clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
  ARM: dts: exynos: Enable DMA support for UART modules on Exynos5 SoCs
  ARM: dts: exynos: Cleanup Odroid-X2 and enable sound on Odroid-X
  ARM: dts: exynos: Fix initial audio clocks configuration on Exynos4 boards
  ARM: dts: exynos: Correct clocks for Exynos4 I2S module

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 71c554ec bca9085e

arch/arm/boot/dts/exynos4.dtsi

+4 −2
Original line number Original line Diff line number Diff line
@@ -64,8 +64,10 @@ 
	i2s0: i2s@03830000 {

	i2s0: i2s@03830000 {

		compatible = "samsung,s5pv210-i2s";

		compatible = "samsung,s5pv210-i2s";

		reg = <0x03830000 0x100>;

		reg = <0x03830000 0x100>;

		clocks = <&clock_audss EXYNOS_I2S_BUS>;

		clocks = <&clock_audss EXYNOS_I2S_BUS>,

		clock-names = "iis";

			 <&clock_audss EXYNOS_DOUT_AUD_BUS>,

			 <&clock_audss EXYNOS_SCLK_I2S>;

		clock-names = "iis", "i2s_opclk0", "i2s_opclk1";

		#clock-cells = <1>;

		#clock-cells = <1>;

		clock-output-names = "i2s_cdclk0";

		clock-output-names = "i2s_cdclk0";

		dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;

		dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;

arch/arm/boot/dts/exynos4212.dtsi

deleted100644 → 0
+0 −133
Original line number Original line Diff line number Diff line 
/*

 * Samsung's Exynos4212 SoC device tree source

 *

 * Copyright (c) 2012 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212

 * based board files can include this file and provide values for board specfic

 * bindings.

 *

 * Note: This file does not include device nodes for all the controllers in

 * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional

 * nodes can be added to this file.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/



#include "exynos4x12.dtsi"



/ {

	compatible = "samsung,exynos4212", "samsung,exynos4";



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@A00 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0xA00>;

			clocks = <&clock CLK_ARM_CLK>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu0_opp_table>;

			cooling-min-level = <13>;

			cooling-max-level = <7>;

			#cooling-cells = <2>; /* min followed by max */

		};



		cpu@A01 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0xA01>;

			operating-points-v2 = <&cpu0_opp_table>;

		};

	};



	cpu0_opp_table: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp00 {

			opp-hz = /bits/ 64 <200000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <200000>;

		};

		opp01 {

			opp-hz = /bits/ 64 <300000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <200000>;

		};

		opp02 {

			opp-hz = /bits/ 64 <400000000>;

			opp-microvolt = <925000>;

			clock-latency-ns = <200000>;

		};

		opp03 {

			opp-hz = /bits/ 64 <500000000>;

			opp-microvolt = <950000>;

			clock-latency-ns = <200000>;

		};

		opp04 {

			opp-hz = /bits/ 64 <600000000>;

			opp-microvolt = <975000>;

			clock-latency-ns = <200000>;

		};

		opp05 {

			opp-hz = /bits/ 64 <700000000>;

			opp-microvolt = <987500>;

			clock-latency-ns = <200000>;

		};

		opp06 {

			opp-hz = /bits/ 64 <800000000>;

			opp-microvolt = <1000000>;

			clock-latency-ns = <200000>;

		};

		opp07 {

			opp-hz = /bits/ 64 <900000000>;

			opp-microvolt = <1037500>;

			clock-latency-ns = <200000>;

		};

		opp08 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <1087500>;

			clock-latency-ns = <200000>;

		};

		opp09 {

			opp-hz = /bits/ 64 <1100000000>;

			opp-microvolt = <1137500>;

			clock-latency-ns = <200000>;

		};

		opp10 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <1187500>;

			clock-latency-ns = <200000>;

		};

		opp11 {

			opp-hz = /bits/ 64 <1300000000>;

			opp-microvolt = <1250000>;

			clock-latency-ns = <200000>;

		};

		opp12 {

			opp-hz = /bits/ 64 <1400000000>;

			opp-microvolt = <1287500>;

			clock-latency-ns = <200000>;

		};

		opp13 {

			opp-hz = /bits/ 64 <1500000000>;

			opp-microvolt = <1350000>;

			clock-latency-ns = <200000>;

			turbo-mode;

		};

	};

};



&combiner {

	samsung,combiner-nr = <18>;

};



&gic {

	cpu-offset = <0x8000>;

};

arch/arm/boot/dts/exynos4412-itop-elite.dts

+10 −15
Original line number Original line Diff line number Diff line
@@ -82,17 +82,6 @@ 
		compatible = "simple-audio-card";

		compatible = "simple-audio-card";

		simple-audio-card,name = "wm-sound";

		simple-audio-card,name = "wm-sound";





		assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,

				<&clock_audss EXYNOS_MOUT_I2S>,

				<&clock_audss EXYNOS_DOUT_SRP>,

				<&clock_audss EXYNOS_DOUT_AUD_BUS>;

		assigned-clock-parents = <&clock CLK_FOUT_EPLL>,

				<&clock_audss EXYNOS_MOUT_AUDSS>;

		assigned-clock-rates = <0>,

				<0>,

				<112896000>,

				<11289600>;



		simple-audio-card,format = "i2s";

		simple-audio-card,format = "i2s";

		simple-audio-card,bitclock-master = <&link0_codec>;

		simple-audio-card,bitclock-master = <&link0_codec>;

		simple-audio-card,frame-master = <&link0_codec>;

		simple-audio-card,frame-master = <&link0_codec>;
@@ -145,6 +134,16 @@ 
	status = "okay";

	status = "okay";

};

};





&clock_audss {

	assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,

			<&clock_audss EXYNOS_MOUT_I2S>,

			<&clock_audss EXYNOS_DOUT_SRP>,

			<&clock_audss EXYNOS_DOUT_AUD_BUS>;

	assigned-clock-parents = <&clock CLK_FOUT_EPLL>,

			<&clock_audss EXYNOS_MOUT_AUDSS>;

	assigned-clock-rates = <0>, <0>, <112896000>, <11289600>;

};



&ehci {

&ehci {

	status = "okay";

	status = "okay";

	/* In order to reset USB ethernet */

	/* In order to reset USB ethernet */
@@ -198,10 +197,6 @@ 
	pinctrl-0 = <&i2s0_bus>;

	pinctrl-0 = <&i2s0_bus>;

	pinctrl-names = "default";

	pinctrl-names = "default";

	status = "okay";

	status = "okay";

	clocks = <&clock_audss EXYNOS_I2S_BUS>,

		 <&clock_audss EXYNOS_DOUT_AUD_BUS>,

		 <&clock_audss EXYNOS_SCLK_I2S>;

	clock-names = "iis", "i2s_opclk0", "i2s_opclk1";

};

};





&pinctrl_1 {

&pinctrl_1 {

arch/arm/boot/dts/exynos4412-odroid-common.dtsi

+12 −16
Original line number Original line Diff line number Diff line
@@ -43,16 +43,6 @@ 




	sound: sound {

	sound: sound {

		compatible = "simple-audio-card";

		compatible = "simple-audio-card";

		assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,

				<&clock_audss EXYNOS_MOUT_I2S>,

				<&clock_audss EXYNOS_DOUT_SRP>,

				<&clock_audss EXYNOS_DOUT_AUD_BUS>;

		assigned-clock-parents = <&clock CLK_FOUT_EPLL>,

				<&clock_audss EXYNOS_MOUT_AUDSS>;

		assigned-clock-rates = <0>,

				<0>,

				<192000000>,

				<19200000>;





		simple-audio-card,format = "i2s";

		simple-audio-card,format = "i2s";

		simple-audio-card,bitclock-master = <&link0_codec>;

		simple-audio-card,bitclock-master = <&link0_codec>;
@@ -97,11 +87,11 @@ 
	thermal-zones {

	thermal-zones {

		cpu_thermal: cpu-thermal {

		cpu_thermal: cpu-thermal {

			cooling-maps {

			cooling-maps {

				map0 {

				cooling_map0: map0 {

				     /* Corresponds to 800MHz at freq_table */

				     /* Corresponds to 800MHz at freq_table */

				     cooling-device = <&cpu0 7 7>;

				     cooling-device = <&cpu0 7 7>;

				};

				};

				map1 {

				cooling_map1: map1 {

				     /* Corresponds to 200MHz at freq_table */

				     /* Corresponds to 200MHz at freq_table */

				     cooling-device = <&cpu0 13 13>;

				     cooling-device = <&cpu0 13 13>;

			       };

			       };
@@ -157,6 +147,16 @@ 
	status = "okay";

	status = "okay";

};

};





&clock_audss {

	assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,

			<&clock_audss EXYNOS_MOUT_I2S>,

			<&clock_audss EXYNOS_DOUT_SRP>,

			<&clock_audss EXYNOS_DOUT_AUD_BUS>;

	assigned-clock-parents = <&clock CLK_FOUT_EPLL>,

			<&clock_audss EXYNOS_MOUT_AUDSS>;

	assigned-clock-rates = <0>, <0>, <192000000>, <19200000>;

};



&cpu0 {

&cpu0 {

	cpu0-supply = <&buck2_reg>;

	cpu0-supply = <&buck2_reg>;

};

};
@@ -503,10 +503,6 @@ 
	pinctrl-0 = <&i2s0_bus>;

	pinctrl-0 = <&i2s0_bus>;

	pinctrl-names = "default";

	pinctrl-names = "default";

	status = "okay";

	status = "okay";

	clocks = <&clock_audss EXYNOS_I2S_BUS>,

		 <&clock_audss EXYNOS_DOUT_AUD_BUS>,

		 <&clock_audss EXYNOS_SCLK_I2S>;

	clock-names = "iis", "i2s_opclk0", "i2s_opclk1";

};

};





&mixer {

&mixer {

arch/arm/boot/dts/exynos4412-odroidu3.dts

+3 −2
Original line number Original line Diff line number Diff line
@@ -13,6 +13,7 @@ 




/dts-v1/;

/dts-v1/;

#include "exynos4412-odroid-common.dtsi"

#include "exynos4412-odroid-common.dtsi"

#include "exynos4412-prime.dtsi"





/ {

/ {

	model = "Hardkernel ODROID-U3 board based on Exynos4412";

	model = "Hardkernel ODROID-U3 board based on Exynos4412";
@@ -47,11 +48,11 @@ 
			cooling-maps {

			cooling-maps {

				map0 {

				map0 {

				     trip = <&cpu_alert1>;

				     trip = <&cpu_alert1>;

				     cooling-device = <&cpu0 7 7>;

				     cooling-device = <&cpu0 9 9>;

				};

				};

				map1 {

				map1 {

				     trip = <&cpu_alert2>;

				     trip = <&cpu_alert2>;

				     cooling-device = <&cpu0 13 13>;

				     cooling-device = <&cpu0 15 15>;

				};

				};

				map2 {

				map2 {

				     trip = <&cpu_alert0>;

				     trip = <&cpu_alert0>;