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Commit 0e0d9dfe authored by Archit Taneja's avatar Archit Taneja Committed by Rob Clark
Browse files

drm/msm/mdp5: Don't get source of MDP core clock 



The driver expects DT to provide the parent to MDP core clock. The only
operation done to the parent clock is to set a rate. This can be
achieved by setting the rate on the core clock itsef. Don't try to
get the parent clock anymore.

Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent cbe4295a

drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c

+2 −5
Original line number Original line Diff line number Diff line
@@ -627,9 +627,6 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) 
	if (ret)

	if (ret)

		goto fail;

		goto fail;

	ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true);

	ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true);

	if (ret)

		goto fail;

	ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src", true);

	if (ret)

	if (ret)

		goto fail;

		goto fail;

	ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true);

	ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true);
@@ -646,7 +643,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) 
	 * rate first, then figure out hw revision, and then set a

	 * rate first, then figure out hw revision, and then set a

	 * more optimal rate:

	 * more optimal rate:

	 */

	 */

	clk_set_rate(mdp5_kms->src_clk, 200000000);

	clk_set_rate(mdp5_kms->core_clk, 200000000);





	read_hw_revision(mdp5_kms, &major, &minor);

	read_hw_revision(mdp5_kms, &major, &minor);
@@ -661,7 +658,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) 
	mdp5_kms->caps = config->hw->mdp.caps;

	mdp5_kms->caps = config->hw->mdp.caps;





	/* TODO: compute core clock rate at runtime */

	/* TODO: compute core clock rate at runtime */

	clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk);

	clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);





	/*

	/*

	 * Some chipsets have a Shared Memory Pool (SMP), while others

	 * Some chipsets have a Shared Memory Pool (SMP), while others

drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -49,7 +49,6 @@ struct mdp5_kms { 




	struct clk *axi_clk;

	struct clk *axi_clk;

	struct clk *ahb_clk;

	struct clk *ahb_clk;

	struct clk *src_clk;

	struct clk *core_clk;

	struct clk *core_clk;

	struct clk *lut_clk;

	struct clk *lut_clk;

	struct clk *vsync_clk;

	struct clk *vsync_clk;