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Commit 0dd532eb authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'rockchip-internal-phy' 



David Wu says:

====================
rockchip: Add the integrated PHY support

The rk3228 and rk3328 support integrated PHY inside, let's enable
it to work. And the integrated PHY need to do some special setting,
so register the rockchip integrated PHY driver.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents d24d39d9 4b05bc61

Documentation/devicetree/bindings/net/phy.txt

+5 −0
Original line number Diff line number Diff line
@@ -52,6 +52,11 @@ Optional Properties: 
  Mark the corresponding energy efficient ethernet mode as broken and

  request the ethernet to stop advertising it.



- phy-is-integrated: If set, indicates that the PHY is integrated into the same

  physical package as the Ethernet MAC. If needed, muxers should be configured

  to ensure the integrated PHY is used. The absence of this property indicates

  the muxers should be configured so that the external PHY is used.



Example:



ethernet-phy@0 {

arch/arm/boot/dts/rk3228-evb.dts

+34 −0
Original line number Diff line number Diff line
@@ -50,6 +50,16 @@ 
		device_type = "memory";

		reg = <0x60000000 0x40000000>;

	};



	vcc_phy: vcc-phy-regulator {

		compatible = "regulator-fixed";

		enable-active-high;

		regulator-name = "vcc_phy";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;

		regulator-always-on;

		regulator-boot-on;

	};

};



&emmc {
@@ -60,6 +70,30 @@ 
	status = "okay";

};



&gmac {

	assigned-clocks = <&cru SCLK_MAC_SRC>;

	assigned-clock-rates = <50000000>;

	clock_in_out = "output";

	phy-supply = <&vcc_phy>;

	phy-mode = "rmii";

	phy-handle = <&phy0>;

	status = "okay";



	mdio {

		compatible = "snps,dwmac-mdio";

		#address-cells = <1>;

		#size-cells = <0>;



		phy@0 {

			compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";

			reg = <0>;

			clocks = <&cru SCLK_MAC_PHY>;

			resets = <&cru SRST_MACPHY>;

			phy-is-integrated;

		};

	};

};



&tsadc {

	status = "okay";

arch/arm/configs/multi_v7_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -270,6 +270,7 @@ CONFIG_ICPLUS_PHY=y 
CONFIG_REALTEK_PHY=y

CONFIG_MICREL_PHY=y

CONFIG_FIXED_PHY=y

CONFIG_ROCKCHIP_PHY=y

CONFIG_USB_PEGASUS=y

CONFIG_USB_RTL8152=m

CONFIG_USB_USBNET=y

arch/arm64/boot/dts/rockchip/rk3328-evb.dts

+17 −0
Original line number Diff line number Diff line
@@ -50,6 +50,23 @@ 
	chosen {

		stdout-path = "serial2:1500000n8";

	};



	vcc_phy: vcc-phy-regulator {

		compatible = "regulator-fixed";

		regulator-name = "vcc_phy";

		regulator-always-on;

		regulator-boot-on;

	};

};



&gmac2phy {

	phy-supply = <&vcc_phy>;

	clock_in_out = "output";

	assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;

	assigned-clock-rate = <50000000>;

	assigned-clocks = <&cru SCLK_MAC2PHY>;

	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;

	status = "okay";

};



&uart2 {

arch/arm64/boot/dts/rockchip/rk3328.dtsi

+39 −0
Original line number Diff line number Diff line
@@ -63,6 +63,8 @@ 
		i2c1 = &i2c1;

		i2c2 = &i2c2;

		i2c3 = &i2c3;

		ethernet0 = &gmac2io;

		ethernet1 = &gmac2phy;

	};



	cpus {
@@ -424,6 +426,43 @@ 
		status = "disabled";

	};



	gmac2phy: ethernet@ff550000 {

		compatible = "rockchip,rk3328-gmac";

		reg = <0x0 0xff550000 0x0 0x10000>;

		rockchip,grf = <&grf>;

		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "macirq";

		clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,

			 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,

			 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,

			 <&cru SCLK_MAC2PHY_OUT>;

		clock-names = "stmmaceth", "mac_clk_rx",

			      "mac_clk_tx", "clk_mac_ref",

			      "aclk_mac", "pclk_mac",

			      "clk_macphy";

		resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;

		reset-names = "stmmaceth", "mac-phy";

		phy-mode = "rmii";

		phy-handle = <&phy>;

		status = "disabled";



		mdio {

			compatible = "snps,dwmac-mdio";

			#address-cells = <1>;

			#size-cells = <0>;



			phy: phy@0 {

				compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";

				reg = <0>;

				clocks = <&cru SCLK_MAC2PHY_OUT>;

				resets = <&cru SRST_MACPHY>;

				pinctrl-names = "default";

				pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;

				phy-is-integrated;

			};

		};

	};



	gic: interrupt-controller@ff811000 {

		compatible = "arm,gic-400";

		#interrupt-cells = <3>;