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Commit 0d551c3f authored by Kukjin Kim's avatar Kukjin Kim
Browse files

gpio: samsung: remov s5pc100 related gpio codes 



This patch removes gpio codes for s5pc100 SoC.

Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent b8529ec1

drivers/gpio/gpio-samsung.c

+0 −276
Original line number Diff line number Diff line
@@ -1169,267 +1169,6 @@ static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = { 
#endif

};



/*

 * S5PC100 GPIO bank summary:

 *

 * Bank	GPIOs	Style	INT Type

 * A0	8	4Bit	GPIO_INT0

 * A1	5	4Bit	GPIO_INT1

 * B	8	4Bit	GPIO_INT2

 * C	5	4Bit	GPIO_INT3

 * D	7	4Bit	GPIO_INT4

 * E0	8	4Bit	GPIO_INT5

 * E1	6	4Bit	GPIO_INT6

 * F0	8	4Bit	GPIO_INT7

 * F1	8	4Bit	GPIO_INT8

 * F2	8	4Bit	GPIO_INT9

 * F3	4	4Bit	GPIO_INT10

 * G0	8	4Bit	GPIO_INT11

 * G1	3	4Bit	GPIO_INT12

 * G2	7	4Bit	GPIO_INT13

 * G3	7	4Bit	GPIO_INT14

 * H0	8	4Bit	WKUP_INT

 * H1	8	4Bit	WKUP_INT

 * H2	8	4Bit	WKUP_INT

 * H3	8	4Bit	WKUP_INT

 * I	8	4Bit	GPIO_INT15

 * J0	8	4Bit	GPIO_INT16

 * J1	5	4Bit	GPIO_INT17

 * J2	8	4Bit	GPIO_INT18

 * J3	8	4Bit	GPIO_INT19

 * J4	4	4Bit	GPIO_INT20

 * K0	8	4Bit	None

 * K1	6	4Bit	None

 * K2	8	4Bit	None

 * K3	8	4Bit	None

 * L0	8	4Bit	None

 * L1	8	4Bit	None

 * L2	8	4Bit	None

 * L3	8	4Bit	None

 */



static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {

#ifdef CONFIG_CPU_S5PC100

	{

		.chip	= {

			.base	= S5PC100_GPA0(0),

			.ngpio	= S5PC100_GPIO_A0_NR,

			.label	= "GPA0",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPA1(0),

			.ngpio	= S5PC100_GPIO_A1_NR,

			.label	= "GPA1",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPB(0),

			.ngpio	= S5PC100_GPIO_B_NR,

			.label	= "GPB",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPC(0),

			.ngpio	= S5PC100_GPIO_C_NR,

			.label	= "GPC",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPD(0),

			.ngpio	= S5PC100_GPIO_D_NR,

			.label	= "GPD",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPE0(0),

			.ngpio	= S5PC100_GPIO_E0_NR,

			.label	= "GPE0",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPE1(0),

			.ngpio	= S5PC100_GPIO_E1_NR,

			.label	= "GPE1",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPF0(0),

			.ngpio	= S5PC100_GPIO_F0_NR,

			.label	= "GPF0",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPF1(0),

			.ngpio	= S5PC100_GPIO_F1_NR,

			.label	= "GPF1",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPF2(0),

			.ngpio	= S5PC100_GPIO_F2_NR,

			.label	= "GPF2",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPF3(0),

			.ngpio	= S5PC100_GPIO_F3_NR,

			.label	= "GPF3",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPG0(0),

			.ngpio	= S5PC100_GPIO_G0_NR,

			.label	= "GPG0",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPG1(0),

			.ngpio	= S5PC100_GPIO_G1_NR,

			.label	= "GPG1",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPG2(0),

			.ngpio	= S5PC100_GPIO_G2_NR,

			.label	= "GPG2",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPG3(0),

			.ngpio	= S5PC100_GPIO_G3_NR,

			.label	= "GPG3",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPI(0),

			.ngpio	= S5PC100_GPIO_I_NR,

			.label	= "GPI",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPJ0(0),

			.ngpio	= S5PC100_GPIO_J0_NR,

			.label	= "GPJ0",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPJ1(0),

			.ngpio	= S5PC100_GPIO_J1_NR,

			.label	= "GPJ1",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPJ2(0),

			.ngpio	= S5PC100_GPIO_J2_NR,

			.label	= "GPJ2",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPJ3(0),

			.ngpio	= S5PC100_GPIO_J3_NR,

			.label	= "GPJ3",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPJ4(0),

			.ngpio	= S5PC100_GPIO_J4_NR,

			.label	= "GPJ4",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPK0(0),

			.ngpio	= S5PC100_GPIO_K0_NR,

			.label	= "GPK0",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPK1(0),

			.ngpio	= S5PC100_GPIO_K1_NR,

			.label	= "GPK1",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPK2(0),

			.ngpio	= S5PC100_GPIO_K2_NR,

			.label	= "GPK2",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPK3(0),

			.ngpio	= S5PC100_GPIO_K3_NR,

			.label	= "GPK3",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPL0(0),

			.ngpio	= S5PC100_GPIO_L0_NR,

			.label	= "GPL0",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPL1(0),

			.ngpio	= S5PC100_GPIO_L1_NR,

			.label	= "GPL1",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPL2(0),

			.ngpio	= S5PC100_GPIO_L2_NR,

			.label	= "GPL2",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPL3(0),

			.ngpio	= S5PC100_GPIO_L3_NR,

			.label	= "GPL3",

		},

	}, {

		.chip	= {

			.base	= S5PC100_GPL4(0),

			.ngpio	= S5PC100_GPIO_L4_NR,

			.label	= "GPL4",

		},

	}, {

		.base	= (S5P_VA_GPIO + 0xC00),

		.irq_base = IRQ_EINT(0),

		.chip	= {

			.base	= S5PC100_GPH0(0),

			.ngpio	= S5PC100_GPIO_H0_NR,

			.label	= "GPH0",

			.to_irq = samsung_gpiolib_to_irq,

		},

	}, {

		.base	= (S5P_VA_GPIO + 0xC20),

		.irq_base = IRQ_EINT(8),

		.chip	= {

			.base	= S5PC100_GPH1(0),

			.ngpio	= S5PC100_GPIO_H1_NR,

			.label	= "GPH1",

			.to_irq = samsung_gpiolib_to_irq,

		},

	}, {

		.base	= (S5P_VA_GPIO + 0xC40),

		.irq_base = IRQ_EINT(16),

		.chip	= {

			.base	= S5PC100_GPH2(0),

			.ngpio	= S5PC100_GPIO_H2_NR,

			.label	= "GPH2",

			.to_irq = samsung_gpiolib_to_irq,

		},

	}, {

		.base	= (S5P_VA_GPIO + 0xC60),

		.irq_base = IRQ_EINT(24),

		.chip	= {

			.base	= S5PC100_GPH3(0),

			.ngpio	= S5PC100_GPIO_H3_NR,

			.label	= "GPH3",

			.to_irq = samsung_gpiolib_to_irq,

		},

	},

#endif

};



/*

 * Followings are the gpio banks in S5PV210/S5PC110

 *
@@ -1681,21 +1420,6 @@ static __init int samsung_gpiolib_init(void) 
				S3C64XX_VA_GPIO);

		samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,

				ARRAY_SIZE(s3c64xx_gpios_4bit2));

	} else if (soc_is_s5pc100()) {

		group = 0;

		chip = s5pc100_gpios_4bit;

		nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);



		for (i = 0; i < nr_chips; i++, chip++) {

			if (!chip->config) {

				chip->config = &samsung_gpio_cfgs[3];

				chip->group = group++;

			}

		}

		samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);

#if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)

		s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);

#endif

	} else if (soc_is_s5pv210()) {

		group = 0;

		chip = s5pv210_gpios_4bit;