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Commit 0d1da8d7 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add dtsi entries of QMP PHY and USB2PHY for LITO"

parents 5014f0f9 99a341c3

Documentation/devicetree/bindings/usb/qcom,msm-phy.txt

+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ Optional properties: 
 - reg: Address and length of the register set for the device

   Optional regs are:

        "phy_rcal_reg": register address for efuse used for rext calibration

 - qcom,no-rext-present: Set only if external REXT is not present. Default value

   is present.



Example:

	hsphy@f9200000 {

arch/arm64/boot/dts/qcom/lito-rumi.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -32,10 +32,6 @@ 
				     0x0 0x4>;

	};



	usb_nop_phy: usb_nop_phy {

		compatible = "usb-nop-xceiv";

	};



	cxo: bi_tcxo {

		compatible = "fixed-factor-clock";

		clocks = <&xo_board>;
@@ -70,6 +66,12 @@ 
	};

};



&usb2_phy0 {

	hsphy@88e3000 {

		status = "disabled";

	};

};



&qupv3_se8_2uart {

	status = "disabled";

};

arch/arm64/boot/dts/qcom/lito-usb.dtsi

+230 −4
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 */



#include <dt-bindings/clock/qcom,gcc-lito.h>

#include <dt-bindings/phy/qcom,lito-qmp-usb3.h>



&soc {

	/* Primary USB port related controller */
@@ -19,10 +20,10 @@ 
		#size-cells = <1>;

		ranges;



		interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,

			     <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

			     <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,

			     <&pdc 15 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",

				"ss_phy_irq", "dm_hs_phy_irq";

		qcom,use-pdc-interrupts;
@@ -56,6 +57,7 @@ 
			compatible = "snps,dwc3";

			reg = <0x0a600000 0xcd00>;

			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;

			usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;

			linux,sysdev_is_parent;

			snps,disable-clk-gating;

			snps,has-lpm-erratum;
@@ -97,4 +99,228 @@ 
			};

		};

	};



	/* Primary USB port related High Speed PHY */

	usb2_phy0: hsphy@88e3000 {

		compatible = "qcom,usb-hsphy-snps-femto";

		reg = <0x88e3000 0x110>;

		reg-names = "hsusb_phy_base";



		vdd-supply = <&pm8150_l5>;

		vdda18-supply = <&pm8150_l12>;

		vdda33-supply = <&pm8150_l2>;

		qcom,vdd-voltage-level = <0 880000 880000>;



		clocks = <&rpmhcc RPMH_CXO_CLK>;

		clock-names = "ref_clk_src";



		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

		reset-names = "phy_reset";

		qcom,no-rext-present;

	};



	/* Primary USB port related QMP USB DP Combo PHY */

	usb_qmp_dp_phy: ssphy@88e8000 {

		compatible = "qcom,usb-ssphy-qmp-dp-combo";

		reg = <0x88e8000 0x3000>;

		reg-names = "qmp_phy_base";



		vdd-supply = <&pm8150_l5>;

		qcom,vdd-voltage-level = <0 880000 880000>;

		qcom,vdd-max-load-uA = <47000>;

		core-supply = <&pm8150a_l7>;

		qcom,vbus-valid-override;

		qcom,qmp-phy-init-seq =

			/* <reg_offset, value, delay> */

			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0

			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0

			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0

			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0

			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0

			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0

			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0

			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0

			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0

			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0

			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0

			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0

			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0

			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0

			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0

			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0

			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0

			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0

			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0

			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0

			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0

			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0

			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0

			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0

			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x05 0

			USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5 0

			USB3_DP_QSERDES_TXA_LANE_MODE_2 0x2A 0

			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F 0

			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x20 0

			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0

			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x04 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x05 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x05 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0E 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0

			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0

			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0

			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0

			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBF 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xBF 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x3F 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x94 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x0B 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB3 0

			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0

			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0

			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0

			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0

			USB3_DP_QSERDES_RXA_GM_CAL 0x1F 0

			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x05 0

			USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5 0

			USB3_DP_QSERDES_TXB_LANE_MODE_2 0x2A 0

			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F 0

			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x20 0

			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0

			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x04 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x05 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x05 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0E 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0

			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0

			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0

			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0

			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBF 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xBF 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x94 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x0B 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB3 0

			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0

			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0

			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0

			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0

			USB3_DP_QSERDES_RXB_GM_CAL 0x1F 0

			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0

			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0

			USB3_DP_PCS_RX_SIGDET_LVL 0xAA 0

			USB3_DP_PCS_CDR_RESET_TIME 0x0F 0

			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0

			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0

			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0

			USB3_DP_PCS_EQ_CONFIG1 0x4B 0

			USB3_DP_PCS_EQ_CONFIG5 0x10 0

			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0

			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0

			0xffffffff 0xffffffff 0x00>;



		qcom,qmp-phy-reg-offset =

			<USB3_DP_PCS_PCS_STATUS1

			 USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL

			 USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR

			 USB3_DP_PCS_POWER_DOWN_CONTROL

			 USB3_DP_PCS_SW_RESET

			 USB3_DP_PCS_START_CONTROL

			 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */

			 0x2a18 /* USB3_DP_DP_PHY_PD_CTL */

			 USB3_DP_COM_POWER_DOWN_CTRL

			 USB3_DP_COM_SW_RESET

			 USB3_DP_COM_RESET_OVRD_CTRL

			 USB3_DP_COM_PHY_MODE_CTRL

			 USB3_DP_COM_TYPEC_CTRL

			 USB3_DP_COM_SWI_CTRL

			 USB3_DP_PCS_CLAMP_ENABLE

			 USB3_DP_PCS_PCS_STATUS2

			 USB3_DP_PCS_INSIG_SW_CTRL3

			 USB3_DP_PCS_INSIG_MX_CTRL3>;



		clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

			<&rpmhcc RPMH_CXO_CLK>,

			<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;

		clock-names = "aux_clk", "pipe_clk", "ref_clk_src",

				"com_aux_clk";



		resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,

			<&gcc GCC_USB3_PHY_PRIM_BCR>;

		reset-names = "global_phy_reset", "phy_reset";



		status = "disabled";

	};



	usb_audio_qmi_dev {

		compatible = "qcom,usb-audio-qmi-dev";

		iommus = <&apps_smmu 0x140f 0x0>;

		qcom,iommu-dma = "disabled";

		qcom,usb-audio-stream-id = <0xf>;

		qcom,usb-audio-intr-num = <2>;

	};



	usb_nop_phy: usb_nop_phy {

		compatible = "usb-nop-xceiv";

	};

};

drivers/usb/phy/phy-msm-snps-hs.c

+10 −2
Original line number Diff line number Diff line
@@ -85,6 +85,7 @@ struct msm_hsphy { 
	bool			suspended;

	bool			cable_connected;

	bool			dpdm_enable;

	bool			no_rext_present;



	int			*param_override_seq;

	int			param_override_seq_cnt;
@@ -396,8 +397,12 @@ static int msm_hsphy_init(struct usb_phy *uphy) 
				phy->rcal_mask, phy->phy_rcal_reg, rcal_code);

	}



	/* Use external resistor for tuning if efuse is not programmed */

	if (!rcal_code)

	/*

	 * Use external resistor value only if:

	 * a. It is present and

	 * b. efuse is not programmed.

	 */

	if (!phy->no_rext_present && !rcal_code)

		msm_usb_write_readback(phy->base, USB2PHY_USB_PHY_RTUNE_SEL,

			RTUNE_SEL, RTUNE_SEL);
@@ -711,6 +716,9 @@ static int msm_hsphy_probe(struct platform_device *pdev) 
		}

	}



	phy->no_rext_present = of_property_read_bool(dev->of_node,

					"qcom,no-rext-present");



	phy->param_override_seq_cnt = of_property_count_elems_of_size(

					dev->of_node,

					"qcom,param-override-seq",