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Commit 0d14a4d0 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: camera: csiphy: Update csiphy power-up sequence for lito v2" into camera-kernel.lnx.1.0

parents 262cabdc accf6177

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

+3 −3
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */



#include "cam_csiphy_soc.h"
@@ -321,11 +321,11 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, 
		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;

		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2;

		csiphy_dev->ctrl_reg->csiphy_common_reg =

			csiphy_common_reg_1_2;

			csiphy_common_reg_1_2_2;

		csiphy_dev->ctrl_reg->csiphy_reset_reg =

			csiphy_reset_reg_1_2;

		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;

		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2;

		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2_2;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;

		csiphy_dev->is_divisor_32_comp = false;

		csiphy_dev->hw_version = CSIPHY_VERSION_V12;

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h

+24 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _CAM_CSIPHY_1_2_2_HWREG_H_
@@ -8,6 +8,29 @@ 


#include "../cam_csiphy_dev.h"



struct csiphy_reg_parms_t csiphy_v1_2_2 = {

	.mipi_csiphy_interrupt_status0_addr = 0x8B0,

	.mipi_csiphy_interrupt_clear0_addr = 0x858,

	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,

	.csiphy_common_array_size = 8,

	.csiphy_reset_array_size = 5,

	.csiphy_2ph_config_array_size = 18,

	.csiphy_3ph_config_array_size = 33,

	.csiphy_2ph_clock_lane = 0x1,

	.csiphy_2ph_combo_ck_ln = 0x10,

};



struct csiphy_reg_t csiphy_common_reg_1_2_2[] = {

	{0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE},

	{0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x081C, 0x5A, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0884, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x088C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0824, 0x72, 0x00, CSIPHY_2PH_REGS},

};



struct csiphy_reg_t

csiphy_2ph_v1_2_2_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {

	{