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Commit 0ce8428b authored by Mark Brown's avatar Mark Brown
Browse files

Merge tag 'asoc-fix-v4.6-rc5' into asoc-intel

ASoC: Fixes for v4.6

This is a fairly large collection of fixes but almost all driver
specific ones, especially to the new Intel drivers which have had a lot
of recent development.  The one core fix is a change to the debugfs code
to avoid crashes in some relatively unusual configurations.
parents fba0d706 8c0f5510
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+1 −0
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@@ -33,6 +33,7 @@ Björn Steinbrink <B.Steinbrink@gmx.de>
Brian Avery <b.avery@hp.com>
Brian King <brking@us.ibm.com>
Christoph Hellwig <hch@lst.de>
Christophe Ricard <christophe.ricard@gmail.com>
Corey Minyard <minyard@acm.org>
Damian Hobson-Garcia <dhobsong@igel.co.jp>
David Brownell <david-b@pacbell.net>
+12 −17
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What:		/sys/devices/platform/<i2c-demux-name>/cur_master
What:		/sys/devices/platform/<i2c-demux-name>/available_masters
Date:		January 2016
KernelVersion:	4.6
Contact:	Wolfram Sang <wsa@the-dreams.de>
Description:
		Reading the file will give you a list of masters which can be
		selected for a demultiplexed bus. The format is
		"<index>:<name>". Example from a Renesas Lager board:

This file selects the active I2C master for a demultiplexed bus.
		0:/i2c@e6500000 1:/i2c@e6508000

Write 0 there for the first master, 1 for the second etc. Reading the file will
give you a list with the active master marked. Example from a Renesas Lager
board:

root@Lager:~# cat /sys/devices/platform/i2c@8/cur_master
* 0 - /i2c@9
  1 - /i2c@e6520000
  2 - /i2c@e6530000

root@Lager:~# echo 2 > /sys/devices/platform/i2c@8/cur_master

root@Lager:~# cat /sys/devices/platform/i2c@8/cur_master
  0 - /i2c@9
  1 - /i2c@e6520000
* 2 - /i2c@e6530000
What:		/sys/devices/platform/<i2c-demux-name>/current_master
Date:		January 2016
KernelVersion:	4.6
Contact:	Wolfram Sang <wsa@the-dreams.de>
Description:
		This file selects/shows the active I2C master for a demultiplexed
		bus. It uses the <index> value from the file 'available_masters'.
+3 −3
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@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.

Required Properties:
- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
- compatible: has to be "qca,<soctype>-pll" and one of the following
  fallbacks:
  - "qca,ar7100-pll"
  - "qca,ar7240-pll"
@@ -21,8 +21,8 @@ Optional properties:

Example:

	memory-controller@18050000 {
		compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
	pll-controller@18050000 {
		compatible = "qca,ar9132-pll", "qca,ar9130-pll";
		reg = <0x18050000 0x20>;

		clock-names = "ref";
+5 −2
Original line number Diff line number Diff line
@@ -9,7 +9,8 @@ have dual GMAC each represented by a child node..
Required properties:
- compatible: Should be "mediatek,mt7623-eth"
- reg: Address and length of the register set for the device
- interrupts: Should contain the frame engines interrupt
- interrupts: Should contain the three frame engines interrupts in numeric
	order. These are fe_int0, fe_int1 and fe_int2.
- clocks: the clock used by the core
- clock-names: the names of the clock listed in the clocks property. These are
	"ethif", "esw", "gp2", "gp1"
@@ -42,7 +43,9 @@ eth: ethernet@1b100000 {
		 <&ethsys CLK_ETHSYS_GP2>,
		 <&ethsys CLK_ETHSYS_GP1>;
	clock-names = "ethif", "esw", "gp2", "gp1";
	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
		      GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
		      GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
	resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
	reset-names = "eth";
+11 −7
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@@ -8,15 +8,19 @@ Required properties:
	of memory mapped region.
- clock-names: from common clock binding:
	Required elements: "24m"
- rockchip,grf: phandle to the syscon managing the "general register files"
- #phy-cells : from the generic PHY bindings, must be 0;

Example:

grf: syscon@ff770000 {
	compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";

...

	edp_phy: edp-phy {
		compatible = "rockchip,rk3288-dp-phy";
	rockchip,grf = <&grf>;
		clocks = <&cru SCLK_EDP_24M>;
		clock-names = "24m";
		#phy-cells = <0>;
	};
};
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