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Commit 0bcb1d84 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-radeon-lockup' into drm-core-next 

* drm-radeon-lockup:
  drm/radeon/kms: simplify & improve GPU reset V2
  drm/radeon/kms: rename gpu_reset to asic_reset
  drm/radeon/kms: fence cleanup + more reliable GPU lockup detection V4

Conflicts:
	drivers/gpu/drm/radeon/r300.c
parents c9c2625f 90aca4d2

drivers/gpu/drm/radeon/evergreen.c

+7 −1
Original line number Diff line number Diff line
@@ -487,7 +487,13 @@ int evergreen_mc_init(struct radeon_device *rdev) 
	return 0;

}



int evergreen_gpu_reset(struct radeon_device *rdev)

bool evergreen_gpu_is_lockup(struct radeon_device *rdev)

{

	/* FIXME: implement for evergreen */

	return false;

}



int evergreen_asic_reset(struct radeon_device *rdev)

{

	/* FIXME: implement for evergreen */

	return 0;

drivers/gpu/drm/radeon/r100.c

+141 −107
Original line number Diff line number Diff line
@@ -663,26 +663,6 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 
	if (r100_debugfs_cp_init(rdev)) {

		DRM_ERROR("Failed to register debugfs file for CP !\n");

	}

	/* Reset CP */

	tmp = RREG32(RADEON_CP_CSQ_STAT);

	if ((tmp & (1 << 31))) {

		DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);

		WREG32(RADEON_CP_CSQ_MODE, 0);

		WREG32(RADEON_CP_CSQ_CNTL, 0);

		WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);

		tmp = RREG32(RADEON_RBBM_SOFT_RESET);

		mdelay(2);

		WREG32(RADEON_RBBM_SOFT_RESET, 0);

		tmp = RREG32(RADEON_RBBM_SOFT_RESET);

		mdelay(2);

		tmp = RREG32(RADEON_CP_CSQ_STAT);

		if ((tmp & (1 << 31))) {

			DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);

		}

	} else {

		DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);

	}



	if (!rdev->me_fw) {

		r = r100_cp_init_microcode(rdev);

		if (r) {
@@ -787,39 +767,6 @@ void r100_cp_disable(struct radeon_device *rdev) 
	}

}



int r100_cp_reset(struct radeon_device *rdev)

{

	uint32_t tmp;

	bool reinit_cp;

	int i;



	reinit_cp = rdev->cp.ready;

	rdev->cp.ready = false;

	WREG32(RADEON_CP_CSQ_MODE, 0);

	WREG32(RADEON_CP_CSQ_CNTL, 0);

	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);

	(void)RREG32(RADEON_RBBM_SOFT_RESET);

	udelay(200);

	WREG32(RADEON_RBBM_SOFT_RESET, 0);

	/* Wait to prevent race in RBBM_STATUS */

	mdelay(1);

	for (i = 0; i < rdev->usec_timeout; i++) {

		tmp = RREG32(RADEON_RBBM_STATUS);

		if (!(tmp & (1 << 16))) {

			DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",

				 tmp);

			if (reinit_cp) {

				return r100_cp_init(rdev, rdev->cp.ring_size);

			}

			return 0;

		}

		DRM_UDELAY(1);

	}

	tmp = RREG32(RADEON_RBBM_STATUS);

	DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);

	return -1;

}



void r100_cp_commit(struct radeon_device *rdev)

{

	WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
@@ -1733,76 +1680,163 @@ int r100_mc_wait_for_idle(struct radeon_device *rdev) 
	return -1;

}



void r100_gpu_init(struct radeon_device *rdev)

void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)

{

	/* TODO: anythings to do here ? pipes ? */

	r100_hdp_reset(rdev);

	lockup->last_cp_rptr = cp->rptr;

	lockup->last_jiffies = jiffies;

}



/**

 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information

 * @rdev:	radeon device structure

 * @lockup:	r100_gpu_lockup structure holding CP lockup tracking informations

 * @cp:		radeon_cp structure holding CP information

 *

 * We don't need to initialize the lockup tracking information as we will either

 * have CP rptr to a different value of jiffies wrap around which will force

 * initialization of the lockup tracking informations.

 *

 * A possible false positivie is if we get call after while and last_cp_rptr ==

 * the current CP rptr, even if it's unlikely it might happen. To avoid this

 * if the elapsed time since last call is bigger than 2 second than we return

 * false and update the tracking information. Due to this the caller must call

 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported

 * the fencing code should be cautious about that.

 *

 * Caller should write to the ring to force CP to do something so we don't get

 * false positive when CP is just gived nothing to do.

 *

 **/

bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)

{

	unsigned long cjiffies, elapsed;



	cjiffies = jiffies;

	if (!time_after(cjiffies, lockup->last_jiffies)) {

		/* likely a wrap around */

		lockup->last_cp_rptr = cp->rptr;

		lockup->last_jiffies = jiffies;

		return false;

	}

	if (cp->rptr != lockup->last_cp_rptr) {

		/* CP is still working no lockup */

		lockup->last_cp_rptr = cp->rptr;

		lockup->last_jiffies = jiffies;

		return false;

	}

	elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);

	if (elapsed >= 3000) {

		/* very likely the improbable case where current

		 * rptr is equal to last recorded, a while ago, rptr

		 * this is more likely a false positive update tracking

		 * information which should force us to be recall at

		 * latter point

		 */

		lockup->last_cp_rptr = cp->rptr;

		lockup->last_jiffies = jiffies;

		return false;

	}

	if (elapsed >= 1000) {

		dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);

		return true;

	}

	/* give a chance to the GPU ... */

	return false;

}



void r100_hdp_reset(struct radeon_device *rdev)

bool r100_gpu_is_lockup(struct radeon_device *rdev)

{

	uint32_t tmp;

	u32 rbbm_status;

	int r;



	tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;

	tmp |= (7 << 28);

	WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);

	(void)RREG32(RADEON_HOST_PATH_CNTL);

	udelay(200);

	WREG32(RADEON_RBBM_SOFT_RESET, 0);

	WREG32(RADEON_HOST_PATH_CNTL, tmp);

	(void)RREG32(RADEON_HOST_PATH_CNTL);

	rbbm_status = RREG32(R_000E40_RBBM_STATUS);

	if (!G_000E40_GUI_ACTIVE(rbbm_status)) {

		r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);

		return false;

	}

	/* force CP activities */

	r = radeon_ring_lock(rdev, 2);

	if (!r) {

		/* PACKET2 NOP */

		radeon_ring_write(rdev, 0x80000000);

		radeon_ring_write(rdev, 0x80000000);

		radeon_ring_unlock_commit(rdev);

	}

	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);

	return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);

}



int r100_rb2d_reset(struct radeon_device *rdev)

void r100_bm_disable(struct radeon_device *rdev)

{

	uint32_t tmp;

	int i;

	u32 tmp;



	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);

	(void)RREG32(RADEON_RBBM_SOFT_RESET);

	udelay(200);

	WREG32(RADEON_RBBM_SOFT_RESET, 0);

	/* Wait to prevent race in RBBM_STATUS */

	/* disable bus mastering */

	tmp = RREG32(R_000030_BUS_CNTL);

	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);

	mdelay(1);

	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);

	mdelay(1);

	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);

	tmp = RREG32(RADEON_BUS_CNTL);

	mdelay(1);

	pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);

	pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);

	mdelay(1);

	for (i = 0; i < rdev->usec_timeout; i++) {

		tmp = RREG32(RADEON_RBBM_STATUS);

		if (!(tmp & (1 << 26))) {

			DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",

				 tmp);

			return 0;

		}

		DRM_UDELAY(1);

	}

	tmp = RREG32(RADEON_RBBM_STATUS);

	DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);

	return -1;

}



int r100_gpu_reset(struct radeon_device *rdev)

int r100_asic_reset(struct radeon_device *rdev)

{

	uint32_t status;

	struct r100_mc_save save;

	u32 status, tmp;



	/* reset order likely matter */

	status = RREG32(RADEON_RBBM_STATUS);

	/* reset HDP */

	r100_hdp_reset(rdev);

	/* reset rb2d */

	if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {

		r100_rb2d_reset(rdev);

	r100_mc_stop(rdev, &save);

	status = RREG32(R_000E40_RBBM_STATUS);

	if (!G_000E40_GUI_ACTIVE(status)) {

		return 0;

	}

	/* TODO: reset 3D engine */

	status = RREG32(R_000E40_RBBM_STATUS);

	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

	/* stop CP */

	WREG32(RADEON_CP_CSQ_CNTL, 0);

	tmp = RREG32(RADEON_CP_RB_CNTL);

	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);

	WREG32(RADEON_CP_RB_RPTR_WR, 0);

	WREG32(RADEON_CP_RB_WPTR, 0);

	WREG32(RADEON_CP_RB_CNTL, tmp);

	/* save PCI state */

	pci_save_state(rdev->pdev);

	/* disable bus mastering */

	r100_bm_disable(rdev);

	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |

					S_0000F0_SOFT_RESET_RE(1) |

					S_0000F0_SOFT_RESET_PP(1) |

					S_0000F0_SOFT_RESET_RB(1));

	RREG32(R_0000F0_RBBM_SOFT_RESET);

	mdelay(500);

	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);

	mdelay(1);

	status = RREG32(R_000E40_RBBM_STATUS);

	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

	/* reset CP */

	status = RREG32(RADEON_RBBM_STATUS);

	if (status & (1 << 16)) {

		r100_cp_reset(rdev);

	}

	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));

	RREG32(R_0000F0_RBBM_SOFT_RESET);

	mdelay(500);

	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);

	mdelay(1);

	status = RREG32(R_000E40_RBBM_STATUS);

	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

	/* restore PCI & busmastering */

	pci_restore_state(rdev->pdev);

	r100_enable_bm(rdev);

	/* Check if GPU is idle */

	status = RREG32(RADEON_RBBM_STATUS);

	if (status & RADEON_RBBM_ACTIVE) {

		DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);

	if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||

		G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {

		dev_err(rdev->dev, "failed to reset GPU\n");

		rdev->gpu_lockup = true;

		return -1;

	}

	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);

	r100_mc_resume(rdev, &save);

	dev_info(rdev->dev, "GPU reset succeed\n");

	return 0;

}
@@ -3399,7 +3433,7 @@ static int r100_startup(struct radeon_device *rdev) 
	/* Resume clock */

	r100_clock_startup(rdev);

	/* Initialize GPU configuration (# pipes, ...) */

	r100_gpu_init(rdev);

//	r100_gpu_init(rdev);

	/* Initialize GART (initialize after TTM so we can allocate

	 * memory through TTM but finalize after TTM) */

	r100_enable_bm(rdev);
@@ -3436,7 +3470,7 @@ int r100_resume(struct radeon_device *rdev) 
	/* Resume clock before doing reset */

	r100_clock_startup(rdev);

	/* Reset gpu before posting otherwise ATOM will enter infinite loop */

	if (radeon_gpu_reset(rdev)) {

	if (radeon_asic_reset(rdev)) {

		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",

			RREG32(R_000E40_RBBM_STATUS),

			RREG32(R_0007C0_CP_STAT));
@@ -3505,7 +3539,7 @@ int r100_init(struct radeon_device *rdev) 
			return r;

	}

	/* Reset gpu before posting otherwise ATOM will enter infinite loop */

	if (radeon_gpu_reset(rdev)) {

	if (radeon_asic_reset(rdev)) {

		dev_warn(rdev->dev,

			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",

			RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/r100d.h

+128 −0
Original line number Diff line number Diff line
@@ -74,6 +74,134 @@ 
#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)



/* Registers */

#define R_0000F0_RBBM_SOFT_RESET                     0x0000F0

#define   S_0000F0_SOFT_RESET_CP(x)                    (((x) & 0x1) << 0)

#define   G_0000F0_SOFT_RESET_CP(x)                    (((x) >> 0) & 0x1)

#define   C_0000F0_SOFT_RESET_CP                       0xFFFFFFFE

#define   S_0000F0_SOFT_RESET_HI(x)                    (((x) & 0x1) << 1)

#define   G_0000F0_SOFT_RESET_HI(x)                    (((x) >> 1) & 0x1)

#define   C_0000F0_SOFT_RESET_HI                       0xFFFFFFFD

#define   S_0000F0_SOFT_RESET_SE(x)                    (((x) & 0x1) << 2)

#define   G_0000F0_SOFT_RESET_SE(x)                    (((x) >> 2) & 0x1)

#define   C_0000F0_SOFT_RESET_SE                       0xFFFFFFFB

#define   S_0000F0_SOFT_RESET_RE(x)                    (((x) & 0x1) << 3)

#define   G_0000F0_SOFT_RESET_RE(x)                    (((x) >> 3) & 0x1)

#define   C_0000F0_SOFT_RESET_RE                       0xFFFFFFF7

#define   S_0000F0_SOFT_RESET_PP(x)                    (((x) & 0x1) << 4)

#define   G_0000F0_SOFT_RESET_PP(x)                    (((x) >> 4) & 0x1)

#define   C_0000F0_SOFT_RESET_PP                       0xFFFFFFEF

#define   S_0000F0_SOFT_RESET_E2(x)                    (((x) & 0x1) << 5)

#define   G_0000F0_SOFT_RESET_E2(x)                    (((x) >> 5) & 0x1)

#define   C_0000F0_SOFT_RESET_E2                       0xFFFFFFDF

#define   S_0000F0_SOFT_RESET_RB(x)                    (((x) & 0x1) << 6)

#define   G_0000F0_SOFT_RESET_RB(x)                    (((x) >> 6) & 0x1)

#define   C_0000F0_SOFT_RESET_RB                       0xFFFFFFBF

#define   S_0000F0_SOFT_RESET_HDP(x)                   (((x) & 0x1) << 7)

#define   G_0000F0_SOFT_RESET_HDP(x)                   (((x) >> 7) & 0x1)

#define   C_0000F0_SOFT_RESET_HDP                      0xFFFFFF7F

#define   S_0000F0_SOFT_RESET_MC(x)                    (((x) & 0x1) << 8)

#define   G_0000F0_SOFT_RESET_MC(x)                    (((x) >> 8) & 0x1)

#define   C_0000F0_SOFT_RESET_MC                       0xFFFFFEFF

#define   S_0000F0_SOFT_RESET_AIC(x)                   (((x) & 0x1) << 9)

#define   G_0000F0_SOFT_RESET_AIC(x)                   (((x) >> 9) & 0x1)

#define   C_0000F0_SOFT_RESET_AIC                      0xFFFFFDFF

#define   S_0000F0_SOFT_RESET_VIP(x)                   (((x) & 0x1) << 10)

#define   G_0000F0_SOFT_RESET_VIP(x)                   (((x) >> 10) & 0x1)

#define   C_0000F0_SOFT_RESET_VIP                      0xFFFFFBFF

#define   S_0000F0_SOFT_RESET_DISP(x)                  (((x) & 0x1) << 11)

#define   G_0000F0_SOFT_RESET_DISP(x)                  (((x) >> 11) & 0x1)

#define   C_0000F0_SOFT_RESET_DISP                     0xFFFFF7FF

#define   S_0000F0_SOFT_RESET_CG(x)                    (((x) & 0x1) << 12)

#define   G_0000F0_SOFT_RESET_CG(x)                    (((x) >> 12) & 0x1)

#define   C_0000F0_SOFT_RESET_CG                       0xFFFFEFFF

#define R_000030_BUS_CNTL                            0x000030

#define   S_000030_BUS_DBL_RESYNC(x)                   (((x) & 0x1) << 0)

#define   G_000030_BUS_DBL_RESYNC(x)                   (((x) >> 0) & 0x1)

#define   C_000030_BUS_DBL_RESYNC                      0xFFFFFFFE

#define   S_000030_BUS_MSTR_RESET(x)                   (((x) & 0x1) << 1)

#define   G_000030_BUS_MSTR_RESET(x)                   (((x) >> 1) & 0x1)

#define   C_000030_BUS_MSTR_RESET                      0xFFFFFFFD

#define   S_000030_BUS_FLUSH_BUF(x)                    (((x) & 0x1) << 2)

#define   G_000030_BUS_FLUSH_BUF(x)                    (((x) >> 2) & 0x1)

#define   C_000030_BUS_FLUSH_BUF                       0xFFFFFFFB

#define   S_000030_BUS_STOP_REQ_DIS(x)                 (((x) & 0x1) << 3)

#define   G_000030_BUS_STOP_REQ_DIS(x)                 (((x) >> 3) & 0x1)

#define   C_000030_BUS_STOP_REQ_DIS                    0xFFFFFFF7

#define   S_000030_BUS_PM4_READ_COMBINE_EN(x)          (((x) & 0x1) << 4)

#define   G_000030_BUS_PM4_READ_COMBINE_EN(x)          (((x) >> 4) & 0x1)

#define   C_000030_BUS_PM4_READ_COMBINE_EN             0xFFFFFFEF

#define   S_000030_BUS_WRT_COMBINE_EN(x)               (((x) & 0x1) << 5)

#define   G_000030_BUS_WRT_COMBINE_EN(x)               (((x) >> 5) & 0x1)

#define   C_000030_BUS_WRT_COMBINE_EN                  0xFFFFFFDF

#define   S_000030_BUS_MASTER_DIS(x)                   (((x) & 0x1) << 6)

#define   G_000030_BUS_MASTER_DIS(x)                   (((x) >> 6) & 0x1)

#define   C_000030_BUS_MASTER_DIS                      0xFFFFFFBF

#define   S_000030_BIOS_ROM_WRT_EN(x)                  (((x) & 0x1) << 7)

#define   G_000030_BIOS_ROM_WRT_EN(x)                  (((x) >> 7) & 0x1)

#define   C_000030_BIOS_ROM_WRT_EN                     0xFFFFFF7F

#define   S_000030_BM_DAC_CRIPPLE(x)                   (((x) & 0x1) << 8)

#define   G_000030_BM_DAC_CRIPPLE(x)                   (((x) >> 8) & 0x1)

#define   C_000030_BM_DAC_CRIPPLE                      0xFFFFFEFF

#define   S_000030_BUS_NON_PM4_READ_COMBINE_EN(x)      (((x) & 0x1) << 9)

#define   G_000030_BUS_NON_PM4_READ_COMBINE_EN(x)      (((x) >> 9) & 0x1)

#define   C_000030_BUS_NON_PM4_READ_COMBINE_EN         0xFFFFFDFF

#define   S_000030_BUS_XFERD_DISCARD_EN(x)             (((x) & 0x1) << 10)

#define   G_000030_BUS_XFERD_DISCARD_EN(x)             (((x) >> 10) & 0x1)

#define   C_000030_BUS_XFERD_DISCARD_EN                0xFFFFFBFF

#define   S_000030_BUS_SGL_READ_DISABLE(x)             (((x) & 0x1) << 11)

#define   G_000030_BUS_SGL_READ_DISABLE(x)             (((x) >> 11) & 0x1)

#define   C_000030_BUS_SGL_READ_DISABLE                0xFFFFF7FF

#define   S_000030_BIOS_DIS_ROM(x)                     (((x) & 0x1) << 12)

#define   G_000030_BIOS_DIS_ROM(x)                     (((x) >> 12) & 0x1)

#define   C_000030_BIOS_DIS_ROM                        0xFFFFEFFF

#define   S_000030_BUS_PCI_READ_RETRY_EN(x)            (((x) & 0x1) << 13)

#define   G_000030_BUS_PCI_READ_RETRY_EN(x)            (((x) >> 13) & 0x1)

#define   C_000030_BUS_PCI_READ_RETRY_EN               0xFFFFDFFF

#define   S_000030_BUS_AGP_AD_STEPPING_EN(x)           (((x) & 0x1) << 14)

#define   G_000030_BUS_AGP_AD_STEPPING_EN(x)           (((x) >> 14) & 0x1)

#define   C_000030_BUS_AGP_AD_STEPPING_EN              0xFFFFBFFF

#define   S_000030_BUS_PCI_WRT_RETRY_EN(x)             (((x) & 0x1) << 15)

#define   G_000030_BUS_PCI_WRT_RETRY_EN(x)             (((x) >> 15) & 0x1)

#define   C_000030_BUS_PCI_WRT_RETRY_EN                0xFFFF7FFF

#define   S_000030_BUS_RETRY_WS(x)                     (((x) & 0xF) << 16)

#define   G_000030_BUS_RETRY_WS(x)                     (((x) >> 16) & 0xF)

#define   C_000030_BUS_RETRY_WS                        0xFFF0FFFF

#define   S_000030_BUS_MSTR_RD_MULT(x)                 (((x) & 0x1) << 20)

#define   G_000030_BUS_MSTR_RD_MULT(x)                 (((x) >> 20) & 0x1)

#define   C_000030_BUS_MSTR_RD_MULT                    0xFFEFFFFF

#define   S_000030_BUS_MSTR_RD_LINE(x)                 (((x) & 0x1) << 21)

#define   G_000030_BUS_MSTR_RD_LINE(x)                 (((x) >> 21) & 0x1)

#define   C_000030_BUS_MSTR_RD_LINE                    0xFFDFFFFF

#define   S_000030_BUS_SUSPEND(x)                      (((x) & 0x1) << 22)

#define   G_000030_BUS_SUSPEND(x)                      (((x) >> 22) & 0x1)

#define   C_000030_BUS_SUSPEND                         0xFFBFFFFF

#define   S_000030_LAT_16X(x)                          (((x) & 0x1) << 23)

#define   G_000030_LAT_16X(x)                          (((x) >> 23) & 0x1)

#define   C_000030_LAT_16X                             0xFF7FFFFF

#define   S_000030_BUS_RD_DISCARD_EN(x)                (((x) & 0x1) << 24)

#define   G_000030_BUS_RD_DISCARD_EN(x)                (((x) >> 24) & 0x1)

#define   C_000030_BUS_RD_DISCARD_EN                   0xFEFFFFFF

#define   S_000030_ENFRCWRDY(x)                        (((x) & 0x1) << 25)

#define   G_000030_ENFRCWRDY(x)                        (((x) >> 25) & 0x1)

#define   C_000030_ENFRCWRDY                           0xFDFFFFFF

#define   S_000030_BUS_MSTR_WS(x)                      (((x) & 0x1) << 26)

#define   G_000030_BUS_MSTR_WS(x)                      (((x) >> 26) & 0x1)

#define   C_000030_BUS_MSTR_WS                         0xFBFFFFFF

#define   S_000030_BUS_PARKING_DIS(x)                  (((x) & 0x1) << 27)

#define   G_000030_BUS_PARKING_DIS(x)                  (((x) >> 27) & 0x1)

#define   C_000030_BUS_PARKING_DIS                     0xF7FFFFFF

#define   S_000030_BUS_MSTR_DISCONNECT_EN(x)           (((x) & 0x1) << 28)

#define   G_000030_BUS_MSTR_DISCONNECT_EN(x)           (((x) >> 28) & 0x1)

#define   C_000030_BUS_MSTR_DISCONNECT_EN              0xEFFFFFFF

#define   S_000030_SERR_EN(x)                          (((x) & 0x1) << 29)

#define   G_000030_SERR_EN(x)                          (((x) >> 29) & 0x1)

#define   C_000030_SERR_EN                             0xDFFFFFFF

#define   S_000030_BUS_READ_BURST(x)                   (((x) & 0x1) << 30)

#define   G_000030_BUS_READ_BURST(x)                   (((x) >> 30) & 0x1)

#define   C_000030_BUS_READ_BURST                      0xBFFFFFFF

#define   S_000030_BUS_RDY_READ_DLY(x)                 (((x) & 0x1) << 31)

#define   G_000030_BUS_RDY_READ_DLY(x)                 (((x) >> 31) & 0x1)

#define   C_000030_BUS_RDY_READ_DLY                    0x7FFFFFFF

#define R_000040_GEN_INT_CNTL                        0x000040

#define   S_000040_CRTC_VBLANK(x)                      (((x) & 0x1) << 0)

#define   G_000040_CRTC_VBLANK(x)                      (((x) >> 0) & 0x1)

drivers/gpu/drm/radeon/r300.c

+82 −74

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/r300d.h

+46 −1
Original line number Diff line number Diff line
@@ -209,7 +209,52 @@ 
#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)

#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)

#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF



#define R_0000F0_RBBM_SOFT_RESET                     0x0000F0

#define   S_0000F0_SOFT_RESET_CP(x)                    (((x) & 0x1) << 0)

#define   G_0000F0_SOFT_RESET_CP(x)                    (((x) >> 0) & 0x1)

#define   C_0000F0_SOFT_RESET_CP                       0xFFFFFFFE

#define   S_0000F0_SOFT_RESET_HI(x)                    (((x) & 0x1) << 1)

#define   G_0000F0_SOFT_RESET_HI(x)                    (((x) >> 1) & 0x1)

#define   C_0000F0_SOFT_RESET_HI                       0xFFFFFFFD

#define   S_0000F0_SOFT_RESET_VAP(x)                   (((x) & 0x1) << 2)

#define   G_0000F0_SOFT_RESET_VAP(x)                   (((x) >> 2) & 0x1)

#define   C_0000F0_SOFT_RESET_VAP                      0xFFFFFFFB

#define   S_0000F0_SOFT_RESET_RE(x)                    (((x) & 0x1) << 3)

#define   G_0000F0_SOFT_RESET_RE(x)                    (((x) >> 3) & 0x1)

#define   C_0000F0_SOFT_RESET_RE                       0xFFFFFFF7

#define   S_0000F0_SOFT_RESET_PP(x)                    (((x) & 0x1) << 4)

#define   G_0000F0_SOFT_RESET_PP(x)                    (((x) >> 4) & 0x1)

#define   C_0000F0_SOFT_RESET_PP                       0xFFFFFFEF

#define   S_0000F0_SOFT_RESET_E2(x)                    (((x) & 0x1) << 5)

#define   G_0000F0_SOFT_RESET_E2(x)                    (((x) >> 5) & 0x1)

#define   C_0000F0_SOFT_RESET_E2                       0xFFFFFFDF

#define   S_0000F0_SOFT_RESET_RB(x)                    (((x) & 0x1) << 6)

#define   G_0000F0_SOFT_RESET_RB(x)                    (((x) >> 6) & 0x1)

#define   C_0000F0_SOFT_RESET_RB                       0xFFFFFFBF

#define   S_0000F0_SOFT_RESET_HDP(x)                   (((x) & 0x1) << 7)

#define   G_0000F0_SOFT_RESET_HDP(x)                   (((x) >> 7) & 0x1)

#define   C_0000F0_SOFT_RESET_HDP                      0xFFFFFF7F

#define   S_0000F0_SOFT_RESET_MC(x)                    (((x) & 0x1) << 8)

#define   G_0000F0_SOFT_RESET_MC(x)                    (((x) >> 8) & 0x1)

#define   C_0000F0_SOFT_RESET_MC                       0xFFFFFEFF

#define   S_0000F0_SOFT_RESET_AIC(x)                   (((x) & 0x1) << 9)

#define   G_0000F0_SOFT_RESET_AIC(x)                   (((x) >> 9) & 0x1)

#define   C_0000F0_SOFT_RESET_AIC                      0xFFFFFDFF

#define   S_0000F0_SOFT_RESET_VIP(x)                   (((x) & 0x1) << 10)

#define   G_0000F0_SOFT_RESET_VIP(x)                   (((x) >> 10) & 0x1)

#define   C_0000F0_SOFT_RESET_VIP                      0xFFFFFBFF

#define   S_0000F0_SOFT_RESET_DISP(x)                  (((x) & 0x1) << 11)

#define   G_0000F0_SOFT_RESET_DISP(x)                  (((x) >> 11) & 0x1)

#define   C_0000F0_SOFT_RESET_DISP                     0xFFFFF7FF

#define   S_0000F0_SOFT_RESET_CG(x)                    (((x) & 0x1) << 12)

#define   G_0000F0_SOFT_RESET_CG(x)                    (((x) >> 12) & 0x1)

#define   C_0000F0_SOFT_RESET_CG                       0xFFFFEFFF

#define   S_0000F0_SOFT_RESET_GA(x)                    (((x) & 0x1) << 13)

#define   G_0000F0_SOFT_RESET_GA(x)                    (((x) >> 13) & 0x1)

#define   C_0000F0_SOFT_RESET_GA                       0xFFFFDFFF

#define   S_0000F0_SOFT_RESET_IDCT(x)                  (((x) & 0x1) << 14)

#define   G_0000F0_SOFT_RESET_IDCT(x)                  (((x) >> 14) & 0x1)

#define   C_0000F0_SOFT_RESET_IDCT                     0xFFFFBFFF



#define R_00000D_SCLK_CNTL                           0x00000D

#define   S_00000D_SCLK_SRC_SEL(x)                     (((x) & 0x7) << 0)