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Commit 0b8c30bc authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon: properly program gart on rv740, juniper, cypress, barts, hemlock 



Need to program an additional VM register.  This doesn't not currently
cause any problems, but allows us to program the proper backend
map in a subsequent patch which should improve performance on these
asics.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 29d65406

drivers/gpu/drm/radeon/evergreen.c

+5 −0
Original line number Diff line number Diff line
@@ -1029,6 +1029,11 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev) 
		WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);

		WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);

		WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);

		if ((rdev->family == CHIP_JUNIPER) ||

		    (rdev->family == CHIP_CYPRESS) ||

		    (rdev->family == CHIP_HEMLOCK) ||

		    (rdev->family == CHIP_BARTS))

			WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);

	}

	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

drivers/gpu/drm/radeon/evergreend.h

+1 −0
Original line number Diff line number Diff line
@@ -452,6 +452,7 @@ 
#define	MC_VM_MD_L1_TLB0_CNTL				0x2654

#define	MC_VM_MD_L1_TLB1_CNTL				0x2658

#define	MC_VM_MD_L1_TLB2_CNTL				0x265C

#define	MC_VM_MD_L1_TLB3_CNTL				0x2698



#define	FUS_MC_VM_MD_L1_TLB0_CNTL			0x265C

#define	FUS_MC_VM_MD_L1_TLB1_CNTL			0x2660

drivers/gpu/drm/radeon/rv770.c

+2 −0
Original line number Diff line number Diff line
@@ -151,6 +151,8 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev) 
	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);

	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);

	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);

	if (rdev->family == CHIP_RV740)

		WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

drivers/gpu/drm/radeon/rv770d.h

+1 −0
Original line number Diff line number Diff line
@@ -174,6 +174,7 @@ 
#define	MC_VM_MD_L1_TLB0_CNTL				0x2654

#define	MC_VM_MD_L1_TLB1_CNTL				0x2658

#define	MC_VM_MD_L1_TLB2_CNTL				0x265C

#define	MC_VM_MD_L1_TLB3_CNTL				0x2698

#define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x203C

#define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2038

#define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2034