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Commit 0b849ee8 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86' of git://git.kernel.org/pub/scm/linux/kernel/git/rric/oprofile into perf/urgent

parents 43948f50 4cafc4b8

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ 
#define MSR_AMD64_IBSDCLINAD		0xc0011038

#define MSR_AMD64_IBSDCPHYSAD		0xc0011039

#define MSR_AMD64_IBSCTL		0xc001103a

#define MSR_AMD64_IBSBRTARGET		0xc001103b



/* Fam 10h MSRs */

#define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058

arch/x86/include/asm/perf_event.h

+10 −9
Original line number Diff line number Diff line
@@ -122,6 +122,7 @@ union cpuid10_edx { 
#define IBS_OP_VAL		(1ULL<<18)

#define IBS_OP_ENABLE		(1ULL<<17)

#define IBS_OP_MAX_CNT		0x0000FFFFULL

#define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */



#ifdef CONFIG_PERF_EVENTS

extern void init_hw_perf_events(void);

arch/x86/oprofile/nmi_int.c

+6 −0
Original line number Diff line number Diff line
@@ -726,6 +726,12 @@ int __init op_nmi_init(struct oprofile_operations *ops) 
		case 0x11:

			cpu_type = "x86-64/family11h";

			break;

		case 0x12:

			cpu_type = "x86-64/family12h";

			break;

		case 0x14:

			cpu_type = "x86-64/family14h";

			break;

		default:

			return -ENODEV;

		}

arch/x86/oprofile/op_model_amd.c

+83 −37
Original line number Diff line number Diff line
@@ -48,17 +48,24 @@ static unsigned long reset_value[NUM_VIRT_COUNTERS]; 


static u32 ibs_caps;



struct op_ibs_config {

struct ibs_config {

	unsigned long op_enabled;

	unsigned long fetch_enabled;

	unsigned long max_cnt_fetch;

	unsigned long max_cnt_op;

	unsigned long rand_en;

	unsigned long dispatched_ops;

	unsigned long branch_target;

};



static struct op_ibs_config ibs_config;

static u64 ibs_op_ctl;

struct ibs_state {

	u64		ibs_op_ctl;

	int		branch_target;

	unsigned long	sample_size;

};



static struct ibs_config ibs_config;

static struct ibs_state ibs_state;



/*

 * IBS cpuid feature detection
@@ -71,8 +78,16 @@ static u64 ibs_op_ctl; 
 * bit 0 is used to indicate the existence of IBS.

 */

#define IBS_CAPS_AVAIL			(1U<<0)

#define IBS_CAPS_FETCHSAM		(1U<<1)

#define IBS_CAPS_OPSAM			(1U<<2)

#define IBS_CAPS_RDWROPCNT		(1U<<3)

#define IBS_CAPS_OPCNT			(1U<<4)

#define IBS_CAPS_BRNTRGT		(1U<<5)

#define IBS_CAPS_OPCNTEXT		(1U<<6)



#define IBS_CAPS_DEFAULT		(IBS_CAPS_AVAIL		\

					 | IBS_CAPS_FETCHSAM	\

					 | IBS_CAPS_OPSAM)



/*

 * IBS APIC setup
@@ -99,12 +114,12 @@ static u32 get_ibs_caps(void) 
	/* check IBS cpuid feature flags */

	max_level = cpuid_eax(0x80000000);

	if (max_level < IBS_CPUID_FEATURES)

		return IBS_CAPS_AVAIL;

		return IBS_CAPS_DEFAULT;



	ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);

	if (!(ibs_caps & IBS_CAPS_AVAIL))

		/* cpuid flags not valid */

		return IBS_CAPS_AVAIL;

		return IBS_CAPS_DEFAULT;



	return ibs_caps;

}
@@ -197,8 +212,8 @@ op_amd_handle_ibs(struct pt_regs * const regs, 
		rdmsrl(MSR_AMD64_IBSOPCTL, ctl);

		if (ctl & IBS_OP_VAL) {

			rdmsrl(MSR_AMD64_IBSOPRIP, val);

			oprofile_write_reserve(&entry, regs, val,

					       IBS_OP_CODE, IBS_OP_SIZE);

			oprofile_write_reserve(&entry, regs, val, IBS_OP_CODE,

					       ibs_state.sample_size);

			oprofile_add_data64(&entry, val);

			rdmsrl(MSR_AMD64_IBSOPDATA, val);

			oprofile_add_data64(&entry, val);
@@ -210,10 +225,14 @@ op_amd_handle_ibs(struct pt_regs * const regs, 
			oprofile_add_data64(&entry, val);

			rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);

			oprofile_add_data64(&entry, val);

			if (ibs_state.branch_target) {

				rdmsrl(MSR_AMD64_IBSBRTARGET, val);

				oprofile_add_data(&entry, (unsigned long)val);

			}

			oprofile_write_commit(&entry);



			/* reenable the IRQ */

			ctl = op_amd_randomize_ibs_op(ibs_op_ctl);

			ctl = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);

			wrmsrl(MSR_AMD64_IBSOPCTL, ctl);

		}

	}
@@ -226,21 +245,32 @@ static inline void op_amd_start_ibs(void) 
	if (!ibs_caps)

		return;



	memset(&ibs_state, 0, sizeof(ibs_state));



	/*

	 * Note: Since the max count settings may out of range we

	 * write back the actual used values so that userland can read

	 * it.

	 */



	if (ibs_config.fetch_enabled) {

		val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT;

		val = ibs_config.max_cnt_fetch >> 4;

		val = min(val, IBS_FETCH_MAX_CNT);

		ibs_config.max_cnt_fetch = val << 4;

		val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;

		val |= IBS_FETCH_ENABLE;

		wrmsrl(MSR_AMD64_IBSFETCHCTL, val);

	}



	if (ibs_config.op_enabled) {

		ibs_op_ctl = ibs_config.max_cnt_op >> 4;

		val = ibs_config.max_cnt_op >> 4;

		if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {

			/*

			 * IbsOpCurCnt not supported.  See

			 * op_amd_randomize_ibs_op() for details.

			 */

			ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);

			val = clamp(val, 0x0081ULL, 0xFF80ULL);

			ibs_config.max_cnt_op = val << 4;

		} else {

			/*

			 * The start value is randomized with a
@@ -248,13 +278,24 @@ static inline void op_amd_start_ibs(void) 
			 * with the half of the randomized range. Also

			 * avoid underflows.

			 */

			ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,

					 IBS_OP_MAX_CNT);

		}

		if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)

			ibs_op_ctl |= IBS_OP_CNT_CTL;

		ibs_op_ctl |= IBS_OP_ENABLE;

		val = op_amd_randomize_ibs_op(ibs_op_ctl);

			val += IBS_RANDOM_MAXCNT_OFFSET;

			if (ibs_caps & IBS_CAPS_OPCNTEXT)

				val = min(val, IBS_OP_MAX_CNT_EXT);

			else

				val = min(val, IBS_OP_MAX_CNT);

			ibs_config.max_cnt_op =

				(val - IBS_RANDOM_MAXCNT_OFFSET) << 4;

		}

		val = ((val & ~IBS_OP_MAX_CNT) << 4) | (val & IBS_OP_MAX_CNT);

		val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;

		val |= IBS_OP_ENABLE;

		ibs_state.ibs_op_ctl = val;

		ibs_state.sample_size = IBS_OP_SIZE;

		if (ibs_config.branch_target) {

			ibs_state.branch_target = 1;

			ibs_state.sample_size++;

		}

		val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);

		wrmsrl(MSR_AMD64_IBSOPCTL, val);

	}

}
@@ -626,12 +667,11 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root) 
	/* model specific files */



	/* setup some reasonable defaults */

	memset(&ibs_config, 0, sizeof(ibs_config));

	ibs_config.max_cnt_fetch = 250000;

	ibs_config.fetch_enabled = 0;

	ibs_config.max_cnt_op = 250000;

	ibs_config.op_enabled = 0;

	ibs_config.dispatched_ops = 0;



	if (ibs_caps & IBS_CAPS_FETCHSAM) {

		dir = oprofilefs_mkdir(sb, root, "ibs_fetch");

		oprofilefs_create_ulong(sb, dir, "enable",

					&ibs_config.fetch_enabled);
@@ -639,7 +679,9 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root) 
					&ibs_config.max_cnt_fetch);

		oprofilefs_create_ulong(sb, dir, "rand_enable",

					&ibs_config.rand_en);

	}



	if (ibs_caps & IBS_CAPS_OPSAM) {

		dir = oprofilefs_mkdir(sb, root, "ibs_op");

		oprofilefs_create_ulong(sb, dir, "enable",

					&ibs_config.op_enabled);
@@ -648,6 +690,10 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root) 
		if (ibs_caps & IBS_CAPS_OPCNT)

			oprofilefs_create_ulong(sb, dir, "dispatched_ops",

						&ibs_config.dispatched_ops);

		if (ibs_caps & IBS_CAPS_BRNTRGT)

			oprofilefs_create_ulong(sb, dir, "branch_target",

						&ibs_config.branch_target);

	}



	return 0;

}