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Commit 0b7c1528 authored by William Cohen's avatar William Cohen Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events aarch64: Add JSON metrics for ARM Cortex-A53 Processor 

Add JSON metrics for ARM Cortex-A53 Processor.

Unlike the Intel processors there isn't a script that automatically
generated these files. The patch was manually generated from the
documentation and the previous oprofile ARM Cortex ac53 event file patch
I made.

The relevant documentation is in the "12.9 Events" section of the ARM
Cortex A53 MPCore Processor Revision: r0p4 Technical Reference Manual.

The ARM Cortex A53 manual is available at:

  http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500g/DDI0500G_cortex_a53_trm.pdf



Use that to look for additional information about the events.

Signed-off-by: default avatarWilliam Cohen <wcohen@redhat.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20180131032813.9564-1-wcohen@redhat.com


[ Added references provided by William Cohen ]
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 7928b2cb

tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json

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+27 −0
Original line number Diff line number Diff line 
[

  {,

    "EventCode": "0x7A",

    "EventName": "BR_INDIRECT_SPEC",

    "BriefDescription": "Branch speculatively executed - Indirect branch"

  },

  {,

    "EventCode": "0xC9",

    "EventName": "BR_COND",

    "BriefDescription": "Conditional branch executed"

  },

  {,

    "EventCode": "0xCA",

    "EventName": "BR_INDIRECT_MISPRED",

    "BriefDescription": "Indirect branch mispredicted"

  },

  {,

    "EventCode": "0xCB",

    "EventName": "BR_INDIRECT_MISPRED_ADDR",

    "BriefDescription": "Indirect branch mispredicted because of address miscompare"

  },

  {,

    "EventCode": "0xCC",

    "EventName": "BR_COND_MISPRED",

    "BriefDescription": "Conditional branch mispredicted"

  }

]

tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json

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+22 −0
Original line number Diff line number Diff line 
[

  {,

    "EventCode": "0x60",

    "EventName": "BUS_ACCESS_LD",

    "BriefDescription": "Bus access - Read"

  },

  {,

    "EventCode": "0x61",

    "EventName": "BUS_ACCESS_ST",

    "BriefDescription": "Bus access - Write"

  },

  {,

    "EventCode": "0xC0",

    "EventName": "EXT_MEM_REQ",

    "BriefDescription": "External memory request"

  },

  {,

    "EventCode": "0xC1",

    "EventName": "EXT_MEM_REQ_NC",

    "BriefDescription": "Non-cacheable external memory request"

  }

]

tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json

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+27 −0
Original line number Diff line number Diff line 
[

  {,

    "EventCode": "0xC2",

    "EventName": "PREFETCH_LINEFILL",

    "BriefDescription": "Linefill because of prefetch"

  },

  {,

    "EventCode": "0xC3",

    "EventName": "PREFETCH_LINEFILL_DROP",

    "BriefDescription": "Instruction Cache Throttle occurred"

  },

  {,

    "EventCode": "0xC4",

    "EventName": "READ_ALLOC_ENTER",

    "BriefDescription": "Entering read allocate mode"

  },

  {,

    "EventCode": "0xC5",

    "EventName": "READ_ALLOC",

    "BriefDescription": "Read allocate mode"

  },

  {,

    "EventCode": "0xC8",

    "EventName": "EXT_SNOOP",

    "BriefDescription": "SCU Snooped data from another CPU for this CPU"

  }

]

tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json

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+22 −0
Original line number Diff line number Diff line 
[

  {,

    "EventCode": "0x60",

    "EventName": "BUS_ACCESS_LD",

    "BriefDescription": "Bus access - Read"

  },

  {,

    "EventCode": "0x61",

    "EventName": "BUS_ACCESS_ST",

    "BriefDescription": "Bus access - Write"

  },

  {,

    "EventCode": "0xC0",

    "EventName": "EXT_MEM_REQ",

    "BriefDescription": "External memory request"

  },

  {,

    "EventCode": "0xC1",

    "EventName": "EXT_MEM_REQ_NC",

    "BriefDescription": "Non-cacheable external memory request"

  }

]

tools/perf/pmu-events/arch/arm64/cortex-a53/other.json

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+32 −0
Original line number Diff line number Diff line 
[

  {,

    "EventCode": "0x86",

    "EventName": "EXC_IRQ",

    "BriefDescription": "Exception taken, IRQ"

  },

  {,

    "EventCode": "0x87",

    "EventName": "EXC_FIQ",

    "BriefDescription": "Exception taken, FIQ"

  },

  {,

    "EventCode": "0xC6",

    "EventName": "PRE_DECODE_ERR",

    "BriefDescription": "Pre-decode error"

  },

  {,

    "EventCode": "0xD0",

    "EventName": "L1I_CACHE_ERR",

    "BriefDescription": "L1 Instruction Cache (data or tag) memory error"

  },

  {,

    "EventCode": "0xD1",

    "EventName": "L1D_CACHE_ERR",

    "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"

  },

  {,

    "EventCode": "0xD2",

    "EventName": "TLB_ERR",

    "BriefDescription": "TLB memory error"

  }

]