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Commit 0b4a2a36 authored by Satheeshakrishna M's avatar Satheeshakrishna M Committed by Daniel Vetter
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drm/i915/bxt: Define BXT power domains 



Add BXT power domains

v2: Use DOMAIN_PLLS instead of a new CDCLK one, whitespace fixes
    (Damien)
v3: add VGA, TRANSCODER_A power domains (imre)

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 9e63743e

drivers/gpu/drm/i915/intel_runtime_pm.c

+55 −0
Original line number Diff line number Diff line
@@ -319,6 +319,38 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, 
	SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) |		\

	BIT(POWER_DOMAIN_INIT))



#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\

	BIT(POWER_DOMAIN_TRANSCODER_A) |		\

	BIT(POWER_DOMAIN_PIPE_B) |			\

	BIT(POWER_DOMAIN_TRANSCODER_B) |		\

	BIT(POWER_DOMAIN_PIPE_C) |			\

	BIT(POWER_DOMAIN_TRANSCODER_C) |		\

	BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |		\

	BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |		\

	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |		\

	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |		\

	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |		\

	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |		\

	BIT(POWER_DOMAIN_AUX_B) |			\

	BIT(POWER_DOMAIN_AUX_C) |			\

	BIT(POWER_DOMAIN_AUDIO) |			\

	BIT(POWER_DOMAIN_VGA) |				\

	BIT(POWER_DOMAIN_INIT))

#define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (		\

	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\

	BIT(POWER_DOMAIN_PIPE_A) |			\

	BIT(POWER_DOMAIN_TRANSCODER_EDP) |		\

	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |		\

	BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |		\

	BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |		\

	BIT(POWER_DOMAIN_AUX_A) |			\

	BIT(POWER_DOMAIN_PLLS) |			\

	BIT(POWER_DOMAIN_INIT))

#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (		\

	(POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |	\

	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |	\

	BIT(POWER_DOMAIN_INIT))



static void skl_set_power_well(struct drm_i915_private *dev_priv,

			struct i915_power_well *power_well, bool enable)

{
@@ -1313,6 +1345,27 @@ static struct i915_power_well skl_power_wells[] = { 
	},

};



static struct i915_power_well bxt_power_wells[] = {

	{

		.name = "always-on",

		.always_on = 1,

		.domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,

		.ops = &i9xx_always_on_power_well_ops,

	},

	{

		.name = "power well 1",

		.domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,

		.ops = &skl_power_well_ops,

		.data = SKL_DISP_PW_1,

	},

	{

		.name = "power well 2",

		.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,

		.ops = &skl_power_well_ops,

		.data = SKL_DISP_PW_2,

	}

};



#define set_power_wells(power_domains, __power_wells) ({		\

	(power_domains)->power_wells = (__power_wells);			\

	(power_domains)->power_well_count = ARRAY_SIZE(__power_wells);	\
@@ -1341,6 +1394,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) 
		set_power_wells(power_domains, bdw_power_wells);

	} else if (IS_SKYLAKE(dev_priv->dev)) {

		set_power_wells(power_domains, skl_power_wells);

	} else if (IS_BROXTON(dev_priv->dev)) {

		set_power_wells(power_domains, bxt_power_wells);

	} else if (IS_CHERRYVIEW(dev_priv->dev)) {

		set_power_wells(power_domains, chv_power_wells);

	} else if (IS_VALLEYVIEW(dev_priv->dev)) {