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Commit 0b043686 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/radeon/kms: make sure pci max read request size is valid on evergreen+ (v2)
  drm/radeon/kms: set a default max_pixel_clock
parents 4d7b5a11 d054ac16

drivers/gpu/drm/radeon/evergreen.c

+27 −0
Original line number Diff line number Diff line
@@ -41,6 +41,31 @@ static void evergreen_gpu_init(struct radeon_device *rdev); 
void evergreen_fini(struct radeon_device *rdev);

static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);



void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)

{

	u16 ctl, v;

	int cap, err;



	cap = pci_pcie_cap(rdev->pdev);

	if (!cap)

		return;



	err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);

	if (err)

		return;



	v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;



	/* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it

	 * to avoid hangs or perfomance issues

	 */

	if ((v == 0) || (v == 6) || (v == 7)) {

		ctl &= ~PCI_EXP_DEVCTL_READRQ;

		ctl |= (2 << 12);

		pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);

	}

}



void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)

{

	/* enable the pflip int */
@@ -1863,6 +1888,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 


	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));



	evergreen_fix_pci_max_read_req_size(rdev);



	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;



	cc_gc_shader_pipe_config |=

drivers/gpu/drm/radeon/ni.c

+3 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 
extern void evergreen_mc_program(struct radeon_device *rdev);

extern void evergreen_irq_suspend(struct radeon_device *rdev);

extern int evergreen_mc_init(struct radeon_device *rdev);

extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);



#define EVERGREEN_PFP_UCODE_SIZE 1120

#define EVERGREEN_PM4_UCODE_SIZE 1376
@@ -669,6 +670,8 @@ static void cayman_gpu_init(struct radeon_device *rdev) 


	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));



	evergreen_fix_pci_max_read_req_size(rdev);



	mc_shared_chmap = RREG32(MC_SHARED_CHMAP);

	mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/radeon_clocks.c

+3 −0
Original line number Diff line number Diff line
@@ -219,6 +219,9 @@ void radeon_get_clock_info(struct drm_device *dev) 
		} else {

			DRM_INFO("Using generic clock info\n");



			/* may need to be per card */

			rdev->clock.max_pixel_clock = 35000;



			if (rdev->flags & RADEON_IS_IGP) {

				p1pll->reference_freq = 1432;

				p2pll->reference_freq = 1432;