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Commit 0af13f70 authored by Elaine Zhang's avatar Elaine Zhang Committed by Heiko Stuebner
Browse files

ARM: dts: rockchip: add qos node for rk3288 



when pd power on/off, the qos regs need to save and restore.

Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 0c744ea4

arch/arm/boot/dts/rk3288.dtsi

+84 −0
Original line number Original line Diff line number Diff line
@@ -762,6 +762,15 @@ 
					 <&cru SCLK_ISP_JPE>,

					 <&cru SCLK_ISP_JPE>,

					 <&cru SCLK_ISP>,

					 <&cru SCLK_ISP>,

					 <&cru SCLK_RGA>;

					 <&cru SCLK_RGA>;

				pm_qos = <&qos_vio0_iep>,

					 <&qos_vio1_vop>,

					 <&qos_vio1_isp_w0>,

					 <&qos_vio1_isp_w1>,

					 <&qos_vio0_vop>,

					 <&qos_vio0_vip>,

					 <&qos_vio2_rga_r>,

					 <&qos_vio2_rga_w>,

					 <&qos_vio1_isp_r>;

			};

			};





			/*

			/*
@@ -773,6 +782,8 @@ 
				clocks = <&cru ACLK_HEVC>,

				clocks = <&cru ACLK_HEVC>,

					 <&cru SCLK_HEVC_CABAC>,

					 <&cru SCLK_HEVC_CABAC>,

					 <&cru SCLK_HEVC_CORE>;

					 <&cru SCLK_HEVC_CORE>;

				pm_qos = <&qos_hevc_r>,

					 <&qos_hevc_w>;

			};

			};





			/*

			/*
@@ -784,6 +795,7 @@ 
				reg = <RK3288_PD_VIDEO>;

				reg = <RK3288_PD_VIDEO>;

				clocks = <&cru ACLK_VCODEC>,

				clocks = <&cru ACLK_VCODEC>,

					 <&cru HCLK_VCODEC>;

					 <&cru HCLK_VCODEC>;

				pm_qos = <&qos_video>;

			};

			};





			/*

			/*
@@ -793,6 +805,8 @@ 
			pd_gpu@RK3288_PD_GPU {

			pd_gpu@RK3288_PD_GPU {

				reg = <RK3288_PD_GPU>;

				reg = <RK3288_PD_GPU>;

				clocks = <&cru ACLK_GPU>;

				clocks = <&cru ACLK_GPU>;

				pm_qos = <&qos_gpu_r>,

					 <&qos_gpu_w>;

			};

			};

		};

		};
@@ -1103,6 +1117,76 @@ 
		};

		};

	};

	};





	qos_gpu_r: qos@ffaa0000 {

		compatible = "syscon";

		reg = <0xffaa0000 0x20>;

	};



	qos_gpu_w: qos@ffaa0080 {

		compatible = "syscon";

		reg = <0xffaa0080 0x20>;

	};



	qos_vio1_vop: qos@ffad0000 {

		compatible = "syscon";

		reg = <0xffad0000 0x20>;

	};



	qos_vio1_isp_w0: qos@ffad0100 {

		compatible = "syscon";

		reg = <0xffad0100 0x20>;

	};



	qos_vio1_isp_w1: qos@ffad0180 {

		compatible = "syscon";

		reg = <0xffad0180 0x20>;

	};



	qos_vio0_vop: qos@ffad0400 {

		compatible = "syscon";

		reg = <0xffad0400 0x20>;

	};



	qos_vio0_vip: qos@ffad0480 {

		compatible = "syscon";

		reg = <0xffad0480 0x20>;

	};



	qos_vio0_iep: qos@ffad0500 {

		compatible = "syscon";

		reg = <0xffad0500 0x20>;

	};



	qos_vio2_rga_r: qos@ffad0800 {

		compatible = "syscon";

		reg = <0xffad0800 0x20>;

	};



	qos_vio2_rga_w: qos@ffad0880 {

		compatible = "syscon";

		reg = <0xffad0880 0x20>;

	};



	qos_vio1_isp_r: qos@ffad0900 {

		compatible = "syscon";

		reg = <0xffad0900 0x20>;

	};



	qos_video: qos@ffae0000 {

		compatible = "syscon";

		reg = <0xffae0000 0x20>;

	};



	qos_hevc_r: qos@ffaf0000 {

		compatible = "syscon";

		reg = <0xffaf0000 0x20>;

	};



	qos_hevc_w: qos@ffaf0080 {

		compatible = "syscon";

		reg = <0xffaf0080 0x20>;

	};



	gic: interrupt-controller@ffc01000 {

	gic: interrupt-controller@ffc01000 {

		compatible = "arm,gic-400";

		compatible = "arm,gic-400";

		interrupt-controller;

		interrupt-controller;