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Commit 0aebff48 authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
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tg3: Fix int generation hw bug for 5719 / 5720 



On the 5719 and 5720, there is a bug where the hardware will
misinterpret a status tag update and leave interrupts permanently
disabled.  This patch enables a hardware fix that works around the
issue.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Reviewed-by: default avatarMichael Chan <mchan@broadcom.com>
Reviewed-by: default avatarBenjamin Li <benli@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent bf734843

drivers/net/tg3.c

+3 −0
Original line number Diff line number Diff line
@@ -8198,6 +8198,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
		      ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;

		if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)

			val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;

		if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&

		    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)

			val |= DMA_RWCTRL_TAGGED_STAT_WA;

		tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);

	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&

		   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {

drivers/net/tg3.h

+1 −0
Original line number Diff line number Diff line
@@ -188,6 +188,7 @@ 
#define   METAL_REV_B2			 0x02

#define TG3PCI_DMA_RW_CTRL		0x0000006c

#define  DMA_RWCTRL_DIS_CACHE_ALIGNMENT  0x00000001

#define  DMA_RWCTRL_TAGGED_STAT_WA	 0x00000080

#define  DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380

#define  DMA_RWCTRL_READ_BNDRY_MASK	 0x00000700

#define  DMA_RWCTRL_READ_BNDRY_DISAB	 0x00000000