Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0aebc6a4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 updates from Catalin Marinas:
 "The main theme of this pull request is security covering variants 2
  and 3 for arm64. I expect to send additional patches next week
  covering an improved firmware interface (requires firmware changes)
  for variant 2 and way for KPTI to be disabled on unaffected CPUs
  (Cavium's ThunderX doesn't work properly with KPTI enabled because of
  a hardware erratum).

  Summary:

   - Security mitigations:
      - variant 2: invalidate the branch predictor with a call to
        secure firmware
      - variant 3: implement KPTI for arm64

   - 52-bit physical address support for arm64 (ARMv8.2)

   - arm64 support for RAS (firmware first only) and SDEI (software
     delegated exception interface; allows firmware to inject a RAS
     error into the OS)

   - perf support for the ARM DynamIQ Shared Unit PMU

   - CPUID and HWCAP bits updated for new floating point multiplication
     instructions in ARMv8.4

   - remove some virtual memory layout printks during boot

   - fix initial page table creation to cope with larger than 32M kernel
     images when 16K pages are enabled"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (104 commits)
  arm64: Fix TTBR + PAN + 52-bit PA logic in cpu_do_switch_mm
  arm64: Turn on KPTI only on CPUs that need it
  arm64: Branch predictor hardening for Cavium ThunderX2
  arm64: Run enable method for errata work arounds on late CPUs
  arm64: Move BP hardening to check_and_switch_context
  arm64: mm: ignore memory above supported physical address size
  arm64: kpti: Fix the interaction between ASID switching and software PAN
  KVM: arm64: Emulate RAS error registers and set HCR_EL2's TERR & TEA
  KVM: arm64: Handle RAS SErrors from EL2 on guest exit
  KVM: arm64: Handle RAS SErrors from EL1 on guest exit
  KVM: arm64: Save ESR_EL2 on guest SError
  KVM: arm64: Save/Restore guest DISR_EL1
  KVM: arm64: Set an impdef ESR for Virtual-SError using VSESR_EL2.
  KVM: arm/arm64: mask/unmask daif around VHE guests
  arm64: kernel: Prepare for a DISR user
  arm64: Unconditionally enable IESB on exception entry/return for firmware-first
  arm64: kernel: Survive corrected RAS errors notified by SError
  arm64: cpufeature: Detect CPU RAS Extentions
  arm64: sysreg: Move to use definitions for all the SCTLR bits
  arm64: cpufeature: __this_cpu_has_cap() shouldn't stop early
  ...
parents 72906f38 ec89ab50

Documentation/arm64/cpu-feature-registers.txt

+3 −1
Original line number Diff line number Diff line
@@ -110,7 +110,9 @@ infrastructure: 
     x--------------------------------------------------x

     | Name                         |  bits   | visible |

     |--------------------------------------------------|

     | RES0                         | [63-48] |    n    |

     | RES0                         | [63-52] |    n    |

     |--------------------------------------------------|

     | FHM                          | [51-48] |    y    |

     |--------------------------------------------------|

     | DP                           | [47-44] |    y    |

     |--------------------------------------------------|

Documentation/arm64/elf_hwcaps.txt

+4 −0
Original line number Diff line number Diff line
@@ -158,3 +158,7 @@ HWCAP_SHA512 
HWCAP_SVE



    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.



HWCAP_ASIMDFHM



   Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001.

Documentation/arm64/silicon-errata.txt

+1 −1
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ stable kernels. 
| Hisilicon      | Hip0{6,7}       | #161010701      | N/A                         |

| Hisilicon      | Hip07           | #161600802      | HISILICON_ERRATUM_161600802 |

|                |                 |                 |                             |

| Qualcomm Tech. | Falkor v1       | E1003           | QCOM_FALKOR_ERRATUM_1003    |

| Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |

| Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |

| Qualcomm Tech. | QDF2400 ITS     | E0065           | QCOM_QDF2400_ERRATUM_0065   |

| Qualcomm Tech. | Falkor v{1,2}   | E1041           | QCOM_FALKOR_ERRATUM_1041    |

Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt

0 → 100644
+27 −0
Original line number Diff line number Diff line 
* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)



ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores

with a shared L3 memory system, control logic and external interfaces to

form a multicore cluster. The PMU enables to gather various statistics on

the operations of the DSU. The PMU provides independent 32bit counters that

can count any of the supported events, along with a 64bit cycle counter.

The PMU is accessed via CPU system registers and has no MMIO component.



** DSU PMU required properties:



- compatible	: should be one of :



		"arm,dsu-pmu"



- interrupts	: Exactly 1 SPI must be listed.



- cpus		: List of phandles for the CPUs connected to this DSU instance.





** Example:



dsu-pmu-0 {

	compatible = "arm,dsu-pmu";

	interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;

	cpus = <&cpu_0>, <&cpu_1>;

};

Documentation/devicetree/bindings/arm/firmware/sdei.txt

0 → 100644
+42 −0
Original line number Diff line number Diff line 
* Software Delegated Exception Interface (SDEI)



Firmware implementing the SDEI functions described in ARM document number

ARM DEN 0054A ("Software Delegated Exception Interface") can be used by

Linux to receive notification of events such as those generated by

firmware-first error handling, or from an IRQ that has been promoted to

a firmware-assisted NMI.



The interface provides a number of API functions for registering callbacks

and enabling/disabling events. Functions are invoked by trapping to the

privilege level of the SDEI firmware (specified as part of the binding

below) and passing arguments in a manner specified by the "SMC Calling

Convention (ARM DEN 0028B):



	 r0		=> 32-bit Function ID / return value

	{r1 - r3}	=> Parameters



Note that the immediate field of the trapping instruction must be set

to #0.



The SDEI_EVENT_REGISTER function registers a callback in the kernel

text to handle the specified event number.



The sdei node should be a child node of '/firmware' and have required

properties:



 - compatible    : should contain:

	* "arm,sdei-1.0" : For implementations complying to SDEI version 1.x.



 - method        : The method of calling the SDEI firmware. Permitted

                   values are:

	* "smc" : SMC #0, with the register assignments specified in this

	          binding.

	* "hvc" : HVC #0, with the register assignments specified in this

	          binding.

Example:

	firmware {

		sdei {

			compatible	= "arm,sdei-1.0";

			method		= "smc";

		};

	};