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Commit 0ab15bde authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-4.7' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

radeon and amdgpu fixes for 4.7.  Highlights:
- fixes for GPU VM passthrough
- fixes for powerplay on Polaris GPUs
- pll fixes for rs780/880

* 'drm-fixes-4.7' of git://people.freedesktop.org/~agd5f/linux:
  drm/amd/powerplay: select samu dpm 0 as boot level on polaris.
  drm/amd/powerplay: update powerplay table parsing
  Revert "drm/amdgpu: add pipeline sync while vmid switch in same ctx"
  drm/amdgpu/gfx7: fix broken condition check
  drm/radeon: fix asic initialization for virtualized environments
  amdgpu: fix asic initialization for virtualized environments (v2)
  drm/radeon: don't use fractional dividers on RS[78]80 if SS is enabled
  drm/radeon: do not hard reset GPU while freezing on r600/r700 family
parents d9724d3b 871fd840

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+8 −3
Original line number Diff line number Diff line
@@ -799,7 +799,6 @@ struct amdgpu_ring { 
	unsigned		cond_exe_offs;

	u64				cond_exe_gpu_addr;

	volatile u32	*cond_exe_cpu_addr;

	int                     vmid;

};



/*
@@ -937,8 +936,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, 
		    unsigned vm_id, uint64_t pd_addr,

		    uint32_t gds_base, uint32_t gds_size,

		    uint32_t gws_base, uint32_t gws_size,

		    uint32_t oa_base, uint32_t oa_size,

		    bool vmid_switch);

		    uint32_t oa_base, uint32_t oa_size);

void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);

uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);

int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
@@ -1822,6 +1820,8 @@ struct amdgpu_asic_funcs { 
	/* MM block clocks */

	int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);

	int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);

	/* query virtual capabilities */

	u32 (*get_virtual_caps)(struct amdgpu_device *adev);

};



/*
@@ -1916,8 +1916,12 @@ void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 




/* GPU virtualization */

#define AMDGPU_VIRT_CAPS_SRIOV_EN       (1 << 0)

#define AMDGPU_VIRT_CAPS_IS_VF          (1 << 1)

struct amdgpu_virtualization {

	bool supports_sr_iov;

	bool is_virtual;

	u32 caps;

};



/*
@@ -2206,6 +2210,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))

#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))

#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))

#define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))

#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))

#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))

#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+16 −1
Original line number Diff line number Diff line
@@ -1385,6 +1385,15 @@ static int amdgpu_resume(struct amdgpu_device *adev) 
	return 0;

}



static bool amdgpu_device_is_virtual(void)

{

#ifdef CONFIG_X86

	return boot_cpu_has(X86_FEATURE_HYPERVISOR);

#else

	return false;

#endif

}



/**

 * amdgpu_device_init - initialize the driver

 *
@@ -1519,8 +1528,14 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	adev->virtualization.supports_sr_iov =

		amdgpu_atombios_has_gpu_virtualization_table(adev);



	/* Check if we are executing in a virtualized environment */

	adev->virtualization.is_virtual = amdgpu_device_is_virtual();

	adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev);



	/* Post card if necessary */

	if (!amdgpu_card_posted(adev)) {

	if (!amdgpu_card_posted(adev) ||

	    (adev->virtualization.is_virtual &&

	     !adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN)) {

		if (!adev->bios) {

			dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");

			return -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

+2 −7
Original line number Diff line number Diff line
@@ -122,7 +122,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
	bool skip_preamble, need_ctx_switch;

	unsigned patch_offset = ~0;

	struct amdgpu_vm *vm;

	int vmid = 0, old_vmid = ring->vmid;

	struct fence *hwf;

	uint64_t ctx;
@@ -136,11 +135,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
	if (job) {

		vm = job->vm;

		ctx = job->ctx;

		vmid = job->vm_id;

	} else {

		vm = NULL;

		ctx = 0;

		vmid = 0;

	}



	if (!ring->ready) {
@@ -166,8 +163,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
		r = amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr,

				    job->gds_base, job->gds_size,

				    job->gws_base, job->gws_size,

				    job->oa_base, job->oa_size,

				    (ring->current_ctx == ctx) && (old_vmid != vmid));

				    job->oa_base, job->oa_size);

		if (r) {

			amdgpu_ring_undo(ring);

			return r;
@@ -184,6 +180,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
	need_ctx_switch = ring->current_ctx != ctx;

	for (i = 0; i < num_ibs; ++i) {

		ib = &ibs[i];



		/* drop preamble IBs if we don't have a context switch */

		if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble)

			continue;
@@ -191,7 +188,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
		amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,

				    need_ctx_switch);

		need_ctx_switch = false;

		ring->vmid = vmid;

	}



	if (ring->funcs->emit_hdp_invalidate)
@@ -202,7 +198,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
		dev_err(adev->dev, "failed to emit fence (%d)\n", r);

		if (job && job->vm_id)

			amdgpu_vm_reset_id(adev, job->vm_id);

		ring->vmid = old_vmid;

		amdgpu_ring_undo(ring);

		return r;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+3 −3
Original line number Diff line number Diff line
@@ -298,8 +298,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, 
		    unsigned vm_id, uint64_t pd_addr,

		    uint32_t gds_base, uint32_t gds_size,

		    uint32_t gws_base, uint32_t gws_size,

		    uint32_t oa_base, uint32_t oa_size,

		    bool vmid_switch)

		    uint32_t oa_base, uint32_t oa_size)

{

	struct amdgpu_device *adev = ring->adev;

	struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
@@ -313,7 +312,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, 
	int r;



	if (ring->funcs->emit_pipeline_sync && (

	    pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed || vmid_switch))

	    pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed ||

		    ring->type == AMDGPU_RING_TYPE_COMPUTE))

		amdgpu_ring_emit_pipeline_sync(ring);



	if (ring->funcs->emit_vm_flush &&

drivers/gpu/drm/amd/amdgpu/cik.c

+7 −0
Original line number Diff line number Diff line
@@ -962,6 +962,12 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev, 
	return true;

}



static u32 cik_get_virtual_caps(struct amdgpu_device *adev)

{

	/* CIK does not support SR-IOV */

	return 0;

}



static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {

	{mmGRBM_STATUS, false},

	{mmGB_ADDR_CONFIG, false},
@@ -2007,6 +2013,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs = 
	.get_xclk = &cik_get_xclk,

	.set_uvd_clocks = &cik_set_uvd_clocks,

	.set_vce_clocks = &cik_set_vce_clocks,

	.get_virtual_caps = &cik_get_virtual_caps,

	/* these should be moved to their own ip modules */

	.get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,

	.wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle,