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Commit 0a4e632b authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-fixes' into clk-next 

* clk-fixes:
  clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle
parents e7cc3335 5dcbeca6

drivers/clk/samsung/clk-exynos4.c

+15 −0
Original line number Diff line number Diff line
@@ -294,6 +294,18 @@ static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { 
#define PLL_ENABLED	(1 << 31)

#define PLL_LOCKED	(1 << 29)



static void exynos4_clk_enable_pll(u32 reg)

{

	u32 pll_con = readl(reg_base + reg);

	pll_con |= PLL_ENABLED;

	writel(pll_con, reg_base + reg);



	while (!(pll_con & PLL_LOCKED)) {

		cpu_relax();

		pll_con = readl(reg_base + reg);

	}

}



static void exynos4_clk_wait_for_pll(u32 reg)

{

	u32 pll_con;
@@ -315,6 +327,9 @@ static int exynos4_clk_suspend(void) 
	samsung_clk_save(reg_base, exynos4_save_pll,

				ARRAY_SIZE(exynos4_clk_pll_regs));



	exynos4_clk_enable_pll(EPLL_CON0);

	exynos4_clk_enable_pll(VPLL_CON0);



	if (exynos4_soc == EXYNOS4210) {

		samsung_clk_save(reg_base, exynos4_save_soc,

					ARRAY_SIZE(exynos4210_clk_save));