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Commit 0a445945 authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915: Work around GCC anonymous union initialization bug 

GCC 4.4 can't cope with anonymous union initializers which seems to be a
bug in that version (see the Reference) and is fixed since GCC version
4.6. A workaround which is also used elsewhere in the kernel for the
same purpose is to wrap the initialization in curly braces, so do the
same here.

Fixes: b5565a2e ("drm/i915/bxt, glk: Give a proper name to the power well struct phy field")
Reference: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10676


Reported-by: default avatarFengguang Wu <fengguang.wu@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170814151530.24154-1-imre.deak@intel.com
parent baa68f6e

drivers/gpu/drm/i915/intel_runtime_pm.c

+54 −24
Original line number Diff line number Diff line
@@ -1920,8 +1920,10 @@ static struct i915_power_well hsw_power_wells[] = { 
		.domains = HSW_DISPLAY_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = HSW_DISP_PW_GLOBAL,

		{

			.hsw.has_vga = true,

		},

	},

};



static struct i915_power_well bdw_power_wells[] = {
@@ -1937,9 +1939,11 @@ static struct i915_power_well bdw_power_wells[] = { 
		.domains = BDW_DISPLAY_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = HSW_DISP_PW_GLOBAL,

		{

			.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

			.hsw.has_vga = true,

		},

	},

};



static const struct i915_power_well_ops vlv_display_power_well_ops = {
@@ -2080,8 +2084,10 @@ static struct i915_power_well skl_power_wells[] = { 
		.domains = 0,

		.ops = &hsw_power_well_ops,

		.id = SKL_DISP_PW_1,

		{

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "MISC IO power well",

		/* Handled by the DMC firmware */
@@ -2100,10 +2106,12 @@ static struct i915_power_well skl_power_wells[] = { 
		.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = SKL_DISP_PW_2,

		{

			.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

			.hsw.has_vga = true,

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "DDI A/E IO power well",

		.domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
@@ -2143,8 +2151,10 @@ static struct i915_power_well bxt_power_wells[] = { 
		.domains = 0,

		.ops = &hsw_power_well_ops,

		.id = SKL_DISP_PW_1,

		{

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "DC off",

		.domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
@@ -2156,24 +2166,30 @@ static struct i915_power_well bxt_power_wells[] = { 
		.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = SKL_DISP_PW_2,

		{

			.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

			.hsw.has_vga = true,

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "dpio-common-a",

		.domains = BXT_DPIO_CMN_A_POWER_DOMAINS,

		.ops = &bxt_dpio_cmn_power_well_ops,

		.id = BXT_DPIO_CMN_A,

		{

			.bxt.phy = DPIO_PHY1,

		},

	},

	{

		.name = "dpio-common-bc",

		.domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,

		.ops = &bxt_dpio_cmn_power_well_ops,

		.id = BXT_DPIO_CMN_BC,

		{

			.bxt.phy = DPIO_PHY0,

		},

	},

};



static struct i915_power_well glk_power_wells[] = {
@@ -2190,8 +2206,10 @@ static struct i915_power_well glk_power_wells[] = { 
		.domains = 0,

		.ops = &hsw_power_well_ops,

		.id = SKL_DISP_PW_1,

		{

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "DC off",

		.domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
@@ -2203,31 +2221,39 @@ static struct i915_power_well glk_power_wells[] = { 
		.domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = SKL_DISP_PW_2,

		{

			.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

			.hsw.has_vga = true,

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "dpio-common-a",

		.domains = GLK_DPIO_CMN_A_POWER_DOMAINS,

		.ops = &bxt_dpio_cmn_power_well_ops,

		.id = BXT_DPIO_CMN_A,

		{

			.bxt.phy = DPIO_PHY1,

		},

	},

	{

		.name = "dpio-common-b",

		.domains = GLK_DPIO_CMN_B_POWER_DOMAINS,

		.ops = &bxt_dpio_cmn_power_well_ops,

		.id = BXT_DPIO_CMN_BC,

		{

			.bxt.phy = DPIO_PHY0,

		},

	},

	{

		.name = "dpio-common-c",

		.domains = GLK_DPIO_CMN_C_POWER_DOMAINS,

		.ops = &bxt_dpio_cmn_power_well_ops,

		.id = GLK_DPIO_CMN_C,

		{

			.bxt.phy = DPIO_PHY2,

		},

	},

	{

		.name = "AUX A",

		.domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
@@ -2280,8 +2306,10 @@ static struct i915_power_well cnl_power_wells[] = { 
		.domains = 0,

		.ops = &hsw_power_well_ops,

		.id = SKL_DISP_PW_1,

		{

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "AUX A",

		.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
@@ -2317,10 +2345,12 @@ static struct i915_power_well cnl_power_wells[] = { 
		.domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = SKL_DISP_PW_2,

		{

			.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

			.hsw.has_vga = true,

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "DDI A IO power well",

		.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,