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Commit 0a09172e authored by Naveen Yadav's avatar Naveen Yadav
Browse files

include: dt-bindings: clock: Update clock IDs supported on Scuba 



Update the clock ids which would be used by consumers to request
on various clocks from various subsystems.

Change-Id: Ic5d29db1ff5885bafd2949b7d5137f3062f9c2fe
Signed-off-by: default avatarNaveen Yadav <naveenky@codeaurora.org>
parent 38ae0c3a

include/dt-bindings/clock/qcom,gcc-scuba.h

+76 −89
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SCUBA_H
@@ -79,17 +79,17 @@ 
#define GCC_CPUSS_THROTTLE_CORE_CLK			69

#define GCC_CPUSS_THROTTLE_XO_CLK			70

#define GCC_DISP_AHB_CLK				71

#define GCC_DISP_GPLL0_DIV_CLK_SRC			72

#define GCC_DISP_HF_AXI_CLK				73

#define GCC_DISP_THROTTLE_CORE_CLK			74

#define GCC_DISP_XO_CLK					75

#define GCC_GP1_CLK					76

#define GCC_GP1_CLK_SRC					77

#define GCC_GP2_CLK					78

#define GCC_GP2_CLK_SRC					79

#define GCC_GP3_CLK					80

#define GCC_GP3_CLK_SRC					81

#define GCC_GPU_BIMC_AXI_CLK_SRC			82

#define GCC_DISP_GPLL0_CLK_SRC				72

#define GCC_DISP_GPLL0_DIV_CLK_SRC			73

#define GCC_DISP_HF_AXI_CLK				74

#define GCC_DISP_THROTTLE_CORE_CLK			75

#define GCC_DISP_XO_CLK					76

#define GCC_GP1_CLK					77

#define GCC_GP1_CLK_SRC					78

#define GCC_GP2_CLK					79

#define GCC_GP2_CLK_SRC					80

#define GCC_GP3_CLK					81

#define GCC_GP3_CLK_SRC					82

#define GCC_GPU_CFG_AHB_CLK				83

#define GCC_GPU_GPLL0_CLK_SRC				84

#define GCC_GPU_GPLL0_DIV_CLK_SRC			85
@@ -98,72 +98,63 @@ 
#define GCC_GPU_SNOC_DVM_GFX_CLK			88

#define GCC_GPU_THROTTLE_CORE_CLK			89

#define GCC_GPU_THROTTLE_XO_CLK				90

#define GCC_MSS_VS_CLK					91

#define GCC_PDM2_CLK					92

#define GCC_PDM2_CLK_SRC				93

#define GCC_PDM_AHB_CLK					94

#define GCC_PDM_XO4_CLK					95

#define GCC_PWM0_XO512_CLK				96

#define GCC_QMIP_CAMERA_NRT_AHB_CLK			97

#define GCC_QMIP_CAMERA_RT_AHB_CLK			98

#define GCC_QMIP_CPUSS_CFG_AHB_CLK			99

#define GCC_QMIP_DISP_AHB_CLK				100

#define GCC_QMIP_GPU_CFG_AHB_CLK			101

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK			102

#define GCC_QUPV3_WRAP0_CORE_2X_CLK			103

#define GCC_QUPV3_WRAP0_CORE_CLK			104

#define GCC_QUPV3_WRAP0_S0_CLK				105

#define GCC_QUPV3_WRAP0_S0_CLK_SRC			106

#define GCC_QUPV3_WRAP0_S1_CLK				107

#define GCC_QUPV3_WRAP0_S1_CLK_SRC			108

#define GCC_QUPV3_WRAP0_S2_CLK				109

#define GCC_QUPV3_WRAP0_S2_CLK_SRC			110

#define GCC_QUPV3_WRAP0_S3_CLK				111

#define GCC_QUPV3_WRAP0_S3_CLK_SRC			112

#define GCC_QUPV3_WRAP0_S4_CLK				113

#define GCC_QUPV3_WRAP0_S4_CLK_SRC			114

#define GCC_QUPV3_WRAP0_S5_CLK				115

#define GCC_QUPV3_WRAP0_S5_CLK_SRC			116

#define GCC_QUPV3_WRAP_0_M_AHB_CLK			117

#define GCC_QUPV3_WRAP_0_S_AHB_CLK			118

#define GCC_SDCC1_AHB_CLK				119

#define GCC_SDCC1_APPS_CLK				120

#define GCC_SDCC1_APPS_CLK_SRC				121

#define GCC_SDCC1_ICE_CORE_CLK				122

#define GCC_SDCC1_ICE_CORE_CLK_SRC			123

#define GCC_SDCC2_AHB_CLK				124

#define GCC_SDCC2_APPS_CLK				125

#define GCC_SDCC2_APPS_CLK_SRC				126

#define GCC_SYS_NOC_CPUSS_AHB_CLK			127

#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK			128

#define GCC_USB30_PRIM_MASTER_CLK			129

#define GCC_USB30_PRIM_MASTER_CLK_SRC			130

#define GCC_USB30_PRIM_MOCK_UTMI_CLK			131

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC		132

#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV		133

#define GCC_USB30_PRIM_SLEEP_CLK			134

#define GCC_USB3_PRIM_CLKREF_CLK			135

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC			136

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK			137

#define GCC_USB3_PRIM_PHY_PIPE_CLK			138

#define GCC_VCODEC0_AXI_CLK				139

#define GCC_VDDA_VS_CLK					140

#define GCC_VDDCX_VS_CLK				141

#define GCC_VDDMX_VS_CLK				142

#define GCC_VENUS_AHB_CLK				143

#define GCC_VENUS_CTL_AXI_CLK				144

#define GCC_VIDEO_AHB_CLK				145

#define GCC_VIDEO_AXI0_CLK				146

#define GCC_VIDEO_THROTTLE_CORE_CLK			147

#define GCC_VIDEO_VCODEC0_SYS_CLK			148

#define GCC_VIDEO_VENUS_CLK_SRC				149

#define GCC_VIDEO_VENUS_CTL_CLK				150

#define GCC_VIDEO_XO_CLK				151

#define GCC_VS_CTRL_AHB_CLK				152

#define GCC_VS_CTRL_CLK					153

#define GCC_VS_CTRL_CLK_SRC				154

#define GCC_VSENSOR_CLK_SRC				155

#define GCC_WCSS_VS_CLK					156

#define GCC_PDM2_CLK					91

#define GCC_PDM2_CLK_SRC				92

#define GCC_PDM_AHB_CLK					93

#define GCC_PDM_XO4_CLK					94

#define GCC_PWM0_XO512_CLK				95

#define GCC_QMIP_CAMERA_NRT_AHB_CLK			96

#define GCC_QMIP_CAMERA_RT_AHB_CLK			97

#define GCC_QMIP_CPUSS_CFG_AHB_CLK			98

#define GCC_QMIP_DISP_AHB_CLK				99

#define GCC_QMIP_GPU_CFG_AHB_CLK			100

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK			101

#define GCC_QUPV3_WRAP0_CORE_2X_CLK			102

#define GCC_QUPV3_WRAP0_CORE_CLK			103

#define GCC_QUPV3_WRAP0_S0_CLK				104

#define GCC_QUPV3_WRAP0_S0_CLK_SRC			105

#define GCC_QUPV3_WRAP0_S1_CLK				106

#define GCC_QUPV3_WRAP0_S1_CLK_SRC			107

#define GCC_QUPV3_WRAP0_S2_CLK				108

#define GCC_QUPV3_WRAP0_S2_CLK_SRC			109

#define GCC_QUPV3_WRAP0_S3_CLK				110

#define GCC_QUPV3_WRAP0_S3_CLK_SRC			111

#define GCC_QUPV3_WRAP0_S4_CLK				112

#define GCC_QUPV3_WRAP0_S4_CLK_SRC			113

#define GCC_QUPV3_WRAP0_S5_CLK				114

#define GCC_QUPV3_WRAP0_S5_CLK_SRC			115

#define GCC_QUPV3_WRAP_0_M_AHB_CLK			116

#define GCC_QUPV3_WRAP_0_S_AHB_CLK			117

#define GCC_SDCC1_AHB_CLK				118

#define GCC_SDCC1_APPS_CLK				119

#define GCC_SDCC1_APPS_CLK_SRC				120

#define GCC_SDCC1_ICE_CORE_CLK				121

#define GCC_SDCC1_ICE_CORE_CLK_SRC			122

#define GCC_SDCC2_AHB_CLK				123

#define GCC_SDCC2_APPS_CLK				124

#define GCC_SDCC2_APPS_CLK_SRC				125

#define GCC_SYS_NOC_CPUSS_AHB_CLK			126

#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK			127

#define GCC_USB30_PRIM_MASTER_CLK			128

#define GCC_USB30_PRIM_MASTER_CLK_SRC			129

#define GCC_USB30_PRIM_MOCK_UTMI_CLK			130

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC		131

#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV		132

#define GCC_USB30_PRIM_SLEEP_CLK			133

#define GCC_USB3_PRIM_CLKREF_CLK			134

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC			135

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK			136

#define GCC_USB3_PRIM_PHY_PIPE_CLK			137

#define GCC_VCODEC0_AXI_CLK				138

#define GCC_VENUS_AHB_CLK				139

#define GCC_VENUS_CTL_AXI_CLK				140

#define GCC_VIDEO_AHB_CLK				141

#define GCC_VIDEO_AXI0_CLK				142

#define GCC_VIDEO_THROTTLE_CORE_CLK			143

#define GCC_VIDEO_VCODEC0_SYS_CLK			144

#define GCC_VIDEO_VENUS_CLK_SRC				145

#define GCC_VIDEO_VENUS_CTL_CLK				146

#define GCC_VIDEO_XO_CLK				147



/* GCC resets */

#define GCC_CAMSS_OPE_BCR				0
@@ -173,16 +164,12 @@ 
#define GCC_MMSS_BCR					4

#define GCC_PDM_BCR					5

#define GCC_QUPV3_WRAPPER_0_BCR				6

#define GCC_QUPV3_WRAPPER_1_BCR				7

#define GCC_QUSB2PHY_PRIM_BCR				8

#define GCC_QUSB2PHY_SEC_BCR				9

#define GCC_SDCC1_BCR					10

#define GCC_SDCC2_BCR					11

#define GCC_USB30_PRIM_BCR				12

#define GCC_USB_PHY_CFG_AHB2PHY_BCR			13

#define GCC_VCODEC0_BCR					14

#define GCC_VENUS_BCR					15

#define GCC_VIDEO_INTERFACE_BCR				16

#define GCC_VS_BCR					17

#define GCC_SDCC1_BCR					7

#define GCC_SDCC2_BCR					8

#define GCC_USB30_PRIM_BCR				9

#define GCC_USB_PHY_CFG_AHB2PHY_BCR			10

#define GCC_VCODEC0_BCR					11

#define GCC_VENUS_BCR					12

#define GCC_VIDEO_INTERFACE_BCR				13



#endif

include/dt-bindings/clock/qcom,gpucc-scuba.h

+12 −12
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SCUBA_H
@@ -10,16 +10,16 @@ 
#define GPU_CC_PLL0				0

#define GPU_CC_AHB_CLK				1

#define GPU_CC_CRC_AHB_CLK			2

#define GPU_CC_CX_APB_CLK			3

#define GPU_CC_CX_GFX3D_CLK			4

#define GPU_CC_CX_GFX3D_SLV_CLK			5

#define GPU_CC_CX_GMU_CLK			6

#define GPU_CC_CX_SNOC_DVM_CLK			7

#define GPU_CC_CXO_AON_CLK			8

#define GPU_CC_CXO_CLK				9

#define GPU_CC_GMU_CLK_SRC			10

#define GPU_CC_GX_CXO_CLK			11

#define GPU_CC_GX_GFX3D_CLK			12

#define GPU_CC_SLEEP_CLK			13

#define GPU_CC_CX_GFX3D_CLK			3

#define GPU_CC_CX_GMU_CLK			4

#define GPU_CC_CX_SNOC_DVM_CLK			5

#define GPU_CC_CXO_AON_CLK			6

#define GPU_CC_CXO_CLK				7

#define GPU_CC_GMU_CLK_SRC			8

#define GPU_CC_GX_CXO_CLK			9

#define GPU_CC_GX_GFX3D_CLK			10

#define GPU_CC_GX_GFX3D_CLK_SRC			11

#define GPU_CC_SLEEP_CLK			12

#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		13



#endif