drm/amdgpu: add initial uvd 7.0 support for vega10 (09bfb891) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/gpu/drm/amd/amdgpu/Makefile

+2 −1

Original line number	Diff line number	Diff line
		@@ -78,7 +78,8 @@ amdgpu-y += \
		amdgpu-y += \
		amdgpu_uvd.o \
		uvd_v5_0.o \
		uvd_v6_0.o
		uvd_v6_0.o \
		uvd_v7_0.o

		# add VCE block
		amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

+41 −11

Original line number	Diff line number	Diff line
		@@ -67,6 +67,14 @@
		#define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"
		#define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin"

		#define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin"

		#define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00)
		#define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00)
		#define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00)
		#define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00)
		#define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00)

		/**
		* amdgpu_uvd_cs_ctx - Command submission parser context
		*
		@@ -101,6 +109,8 @@ MODULE_FIRMWARE(FIRMWARE_POLARIS10);
		MODULE_FIRMWARE(FIRMWARE_POLARIS11);
		MODULE_FIRMWARE(FIRMWARE_POLARIS12);

		MODULE_FIRMWARE(FIRMWARE_VEGA10);

		static void amdgpu_uvd_idle_work_handler(struct work_struct *work);

		int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
		@@ -151,6 +161,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
		case CHIP_POLARIS11:
		fw_name = FIRMWARE_POLARIS11;
		break;
		case CHIP_VEGA10:
		fw_name = FIRMWARE_VEGA10;
		break;
		case CHIP_POLARIS12:
		fw_name = FIRMWARE_POLARIS12;
		break;
		@@ -203,9 +216,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
		DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
		version_major, version_minor);

		bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
		+ AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
		bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
		+ AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
		if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);

		r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
		AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo,
		&adev->uvd.gpu_addr, &adev->uvd.cpu_addr);
		@@ -319,11 +334,13 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
		unsigned offset;

		hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
		if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
		offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
		memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset,
		le32_to_cpu(hdr->ucode_size_bytes));
		size -= le32_to_cpu(hdr->ucode_size_bytes);
		ptr += le32_to_cpu(hdr->ucode_size_bytes);
		}
		memset_io(ptr, 0, size);
		}

		@@ -936,6 +953,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring ring, struct amdgpu_bo bo,
		struct dma_fence *f = NULL;
		struct amdgpu_device *adev = ring->adev;
		uint64_t addr;
		uint32_t data[4];
		int i, r;

		memset(&tv, 0, sizeof(tv));
		@@ -961,16 +979,28 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring ring, struct amdgpu_bo bo,
		if (r)
		goto err;

		if (adev->asic_type >= CHIP_VEGA10) {
		data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0);
		data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0);
		data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0);
		data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0);
		} else {
		data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
		data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
		data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
		data[3] = PACKET0(mmUVD_NO_OP, 0);
		}

		ib = &job->ibs[0];
		addr = amdgpu_bo_gpu_offset(bo);
		ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
		ib->ptr[0] = data[0];
		ib->ptr[1] = addr;
		ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
		ib->ptr[2] = data[1];
		ib->ptr[3] = addr >> 32;
		ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
		ib->ptr[4] = data[2];
		ib->ptr[5] = 0;
		for (i = 6; i < 16; i += 2) {
		ib->ptr[i] = PACKET0(mmUVD_NO_OP, 0);
		ib->ptr[i] = data[3];
		ib->ptr[i+1] = 0;
		}
		ib->length_dw = 16;

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

0 → 100644

+1543 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h

0 → 100644

+29 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2016 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		*/

		#ifndef __UVD_V7_0_H__
		#define __UVD_V7_0_H__

		extern const struct amdgpu_ip_block_version uvd_v7_0_ip_block;

		#endif