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Commit 08dfcae1 authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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clk: qcom: lito: Update the PLL settings for Lucid/Zonda PLL 



The PLL register configuration requires to be updated as per the hardware
recommendation.

Change-Id: I958683b5b95b43719604a3f8aee97ef55184da12
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 9b7165c0

drivers/clk/qcom/camcc-lito.c

+14 −10
Original line number Diff line number Diff line
@@ -197,10 +197,11 @@ static const struct alpha_pll_config cam_cc_pll0_config = { 
	.alpha = 0x8000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.user_ctl_val = 0x00000007,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000001,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

};



static struct clk_alpha_pll cam_cc_pll0 = {
@@ -273,10 +274,11 @@ static const struct alpha_pll_config cam_cc_pll1_config = { 
	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.user_ctl_val = 0x00000007,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000001,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

};



static struct clk_alpha_pll cam_cc_pll1 = {
@@ -327,9 +329,9 @@ static const struct alpha_pll_config cam_cc_pll2_config = { 
	.cal_l = 0x32,

	.alpha = 0x0,

	.config_ctl_val = 0x08200920,

	.config_ctl_hi_val = 0x05008011,

	.config_ctl_hi_val = 0x15008001,

	.config_ctl_hi1_val = 0x00000000,

	.user_ctl_val = 0x0000010F,

	.user_ctl_val = 0xE0000101,

	.test_ctl_val = 0x00010000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x00000000,
@@ -405,10 +407,11 @@ static const struct alpha_pll_config cam_cc_pll3_config = { 
	.alpha = 0x9555,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.user_ctl_val = 0x00000007,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000001,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

};



static struct clk_alpha_pll cam_cc_pll3 = {
@@ -460,10 +463,11 @@ static const struct alpha_pll_config cam_cc_pll4_config = { 
	.alpha = 0x9555,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.user_ctl_val = 0x00000007,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000001,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

};



static struct clk_alpha_pll cam_cc_pll4 = {

drivers/clk/qcom/dispcc-lito.c

+2 −1
Original line number Diff line number Diff line
@@ -149,10 +149,11 @@ static const struct alpha_pll_config disp_cc_pll0_config = { 
	.alpha = 0xE000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000001,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

};



static struct clk_alpha_pll disp_cc_pll0 = {

drivers/clk/qcom/gpucc-lito.c

+2 −1
Original line number Diff line number Diff line
@@ -73,10 +73,11 @@ static const struct alpha_pll_config gpu_cc_pll1_config = { 
	.alpha = 0xAAA,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000001,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

};



static struct clk_alpha_pll gpu_cc_pll1 = {

drivers/clk/qcom/npucc-lito.c

+7 −4
Original line number Diff line number Diff line
@@ -118,14 +118,15 @@ static const u32 crc_reg_val[] = { 


static struct alpha_pll_config npu_cc_pll0_config = {

	.l = 0x14,

	.cal_l = 0x44,

	.cal_l = 0x49,

	.alpha = 0xD555,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.custom_reg_offset = crc_reg_offset,

	.custom_reg_val = crc_reg_val,

	.num_custom_reg = ARRAY_SIZE(crc_reg_offset),
@@ -181,10 +182,11 @@ static struct alpha_pll_config npu_cc_pll1_config = { 
	.alpha = 0xA000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

};



static struct clk_alpha_pll npu_cc_pll1 = {
@@ -237,10 +239,11 @@ static struct alpha_pll_config npu_q6ss_pll_config = { 
	.alpha = 0x555,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

};



static struct clk_alpha_pll npu_q6ss_pll = {

drivers/clk/qcom/videocc-lito.c

+3 −2
Original line number Diff line number Diff line
@@ -89,10 +89,11 @@ static struct alpha_pll_config video_pll0_config = { 
	.alpha = 0x0,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000001,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

};



static struct clk_alpha_pll video_pll0 = {
@@ -482,7 +483,7 @@ static int video_cc_lito_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);

	clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);



	ret = qcom_cc_really_probe(pdev, &video_cc_lito_desc, regmap);

	if (ret) {