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Commit 08c99129 authored by Todd Fujinaka's avatar Todd Fujinaka Committed by Jeff Kirsher
Browse files

igb: use the correct i210 register for EEMNGCTL 



The i210 has two EEPROM access registers that are located in
non-standard offsets: EEARBC and EEMNGCTL. EEARBC was fixed previously
and EEMNGCTL should also be corrected.

Reported-by: default avatarRoman Hodek <roman.aud@siemens.com>
Signed-off-by: default avatarTodd Fujinaka <todd.fujinaka@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent a48954c8

drivers/net/ethernet/intel/igb/e1000_82575.c

+1 −0
Original line number Diff line number Diff line
@@ -299,6 +299,7 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw) 
	case I210_I_PHY_ID:

		phy->type		= e1000_phy_i210;

		phy->ops.check_polarity	= igb_check_polarity_m88;

		phy->ops.get_cfg_done	= igb_get_cfg_done_i210;

		phy->ops.get_phy_info	= igb_get_phy_info_m88;

		phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;

		phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;

drivers/net/ethernet/intel/igb/e1000_i210.c

+27 −0
Original line number Diff line number Diff line
@@ -900,3 +900,30 @@ s32 igb_pll_workaround_i210(struct e1000_hw *hw) 
	wr32(E1000_MDICNFG, mdicnfg);

	return ret_val;

}



/**

 *  igb_get_cfg_done_i210 - Read config done bit

 *  @hw: pointer to the HW structure

 *

 *  Read the management control register for the config done bit for

 *  completion status.  NOTE: silicon which is EEPROM-less will fail trying

 *  to read the config done bit, so an error is *ONLY* logged and returns

 *  0.  If we were to return with error, EEPROM-less silicon

 *  would not be able to be reset or change link.

 **/

s32 igb_get_cfg_done_i210(struct e1000_hw *hw)

{

	s32 timeout = PHY_CFG_TIMEOUT;

	u32 mask = E1000_NVM_CFG_DONE_PORT_0;



	while (timeout) {

		if (rd32(E1000_EEMNGCTL_I210) & mask)

			break;

		usleep_range(1000, 2000);

		timeout--;

	}

	if (!timeout)

		hw_dbg("MNG configuration cycle has not completed.\n");



	return 0;

}

drivers/net/ethernet/intel/igb/e1000_i210.h

+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data); 
s32 igb_init_nvm_params_i210(struct e1000_hw *hw);

bool igb_get_flash_presence_i210(struct e1000_hw *hw);

s32 igb_pll_workaround_i210(struct e1000_hw *hw);

s32 igb_get_cfg_done_i210(struct e1000_hw *hw);



#define E1000_STM_OPCODE		0xDB00

#define E1000_EEPROM_FLASH_SIZE_WORD	0x11

drivers/net/ethernet/intel/igb/e1000_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ 
#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */

#define E1000_PBS      0x01008  /* Packet Buffer Size */

#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */

#define E1000_EEMNGCTL_I210 0x12030  /* MNG EEprom Control */

#define E1000_EEARBC_I210 0x12024  /* EEPROM Auto Read Bus Control */

#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */

#define E1000_I2CCMD   0x01028  /* SFPI2C Command Register - RW */