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Commit 08ba1b8b authored by Rama Aparna Mallavarapu's avatar Rama Aparna Mallavarapu
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ARM: dts: qcom: Add NPU LLCC Bandwidth voting device 

Add the NPU BWMON device to vote for LLCC bandwidth. This
would allow us to independently vote for LLCC and DDR bandwidth
to improve power.

Change-Id: Ib0d9413a4595ff8d66c1e899322bee5bf3a2e30c
parent 97d555bb

qcom/kona.dtsi

+22 −5
Original line number Diff line number Diff line
@@ -1073,14 +1073,14 @@ 
		qcom,count-unit = <0x10000>;

	};



	npu_npu_ddr_bw: qcom,npu-npu-ddr-bw {

	npu_npu_llcc_bw: qcom,npu-npu-llcc-bw {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_LLCC>;

		operating-points-v2 = <&suspendable_llcc_bw_opp_table>;

	};



	npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@60300 {

	npu_npu_llcc_bwmon: qcom,npu-npu-llcc-bwmon@60300 {

		compatible = "qcom,bimc-bwmon4";

		reg = <0x00060400 0x300>, <0x00060300 0x200>;

		reg-names = "base", "global_base";
@@ -1091,7 +1091,24 @@ 
		interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npu_npu_ddr_bw>;

		qcom,target-dev = <&npu_npu_llcc_bw>;

		qcom,count-unit = <0x10000>;

	};



	npu_llcc_ddr_bw: qcom,npu-llcc-ddr-bw {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_SLAVE_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

	};



	npu_llcc_ddr_bwmon: qcom,npu-llcc-ddr-bwmon@0x9092000 {

		compatible = "qcom,bimc-bwmon5";

		reg = <0x9092000 0x1000>;

		reg-names = "base";

		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npu_llcc_ddr_bw>;

		qcom,count-unit = <0x10000>;

	};