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Commit 086e8ced authored by Kenji Kaneshige's avatar Kenji Kaneshige Committed by H. Peter Anvin
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x86, vt-d: Fix the vt-d fault handling irq migration in the x2apic mode 



In x2apic mode, we need to set the upper address register of the fault
handling interrupt register of the vt-d hardware. Without this
irq migration of the vt-d fault handling interrupt is broken.

Signed-off-by: default avatarKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
LKML-Reference: <1291225233.2648.39.camel@sbsiddha-MOBL3>
Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
Cc: stable@kernel.org [v2.6.32+]
Acked-by: default avatarChris Wright <chrisw@sous-sol.org>
Tested-by: default avatarTakao Indoh <indou.takao@jp.fujitsu.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent 254e4200

arch/x86/kernel/apic/io_apic.c

+1 −0
Original line number Diff line number Diff line
@@ -3412,6 +3412,7 @@ dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, 
	msg.data |= MSI_DATA_VECTOR(cfg->vector);

	msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;

	msg.address_lo |= MSI_ADDR_DEST_ID(dest);

	msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);



	dmar_msi_write(irq, &msg);