fw-api: kiwi_v2: Hardware files required for TxMon (08105d29) · Commits · e / devices / android_kernel_fairphone_FP4

hw/kiwi/v2/ack_report.h

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		/*
		* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
		*
		* Permission to use, copy, modify, and/or distribute this software for any
		* purpose with or without fee is hereby granted, provided that the above
		* copyright notice and this permission notice appear in all copies.
		*
		* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
		* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
		* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
		* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
		* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
		* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
		* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
		*/



		#ifndef _ACK_REPORT_H_
		#define _ACK_REPORT_H_
		#if !defined(__ASSEMBLER__)
		#endif

		#define NUM_OF_DWORDS_ACK_REPORT 1

		struct ack_report {
		#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
		uint32_t selfgen_response_reason : 4,
		ax_trigger_type : 4,
		sr_ppdu : 1,
		reserved : 7,
		frame_control : 16;
		#else
		uint32_t frame_control : 16,
		reserved : 7,
		sr_ppdu : 1,
		ax_trigger_type : 4,
		selfgen_response_reason : 4;
		#endif
		};

		#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000
		#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0
		#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3
		#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f

		#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000
		#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4
		#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7
		#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0

		#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000
		#define ACK_REPORT_SR_PPDU_LSB 8
		#define ACK_REPORT_SR_PPDU_MSB 8
		#define ACK_REPORT_SR_PPDU_MASK 0x00000100

		#define ACK_REPORT_RESERVED_OFFSET 0x00000000
		#define ACK_REPORT_RESERVED_LSB 9
		#define ACK_REPORT_RESERVED_MSB 15
		#define ACK_REPORT_RESERVED_MASK 0x0000fe00

		#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
		#define ACK_REPORT_FRAME_CONTROL_LSB 16
		#define ACK_REPORT_FRAME_CONTROL_MSB 31
		#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000

		#endif

hw/kiwi/v2/coex_rx_status.h

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		/*
		* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
		*
		* Permission to use, copy, modify, and/or distribute this software for any
		* purpose with or without fee is hereby granted, provided that the above
		* copyright notice and this permission notice appear in all copies.
		*
		* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
		* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
		* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
		* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
		* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
		* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
		* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
		*/



		#ifndef _COEX_RX_STATUS_H_
		#define _COEX_RX_STATUS_H_
		#if !defined(__ASSEMBLER__)
		#endif

		#define NUM_OF_DWORDS_COEX_RX_STATUS 2

		#define NUM_OF_QWORDS_COEX_RX_STATUS 1

		struct coex_rx_status {
		#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
		uint32_t rx_mac_frame_status : 2,
		rx_with_tx_response : 1,
		rx_rate : 5,
		rx_bw : 3,
		single_mpdu : 1,
		filter_status : 1,
		ampdu : 1,
		directed : 1,
		reserved_0 : 1,
		rx_nss : 3,
		rx_rssi : 8,
		rx_type : 3,
		retry_bit_setting : 1,
		more_data_bit_setting : 1;
		uint32_t remain_rx_packet_time : 16,
		rx_remaining_fes_time : 16;
		#else
		uint32_t more_data_bit_setting : 1,
		retry_bit_setting : 1,
		rx_type : 3,
		rx_rssi : 8,
		rx_nss : 3,
		reserved_0 : 1,
		directed : 1,
		ampdu : 1,
		filter_status : 1,
		single_mpdu : 1,
		rx_bw : 3,
		rx_rate : 5,
		rx_with_tx_response : 1,
		rx_mac_frame_status : 2;
		uint32_t rx_remaining_fes_time : 16,
		remain_rx_packet_time : 16;
		#endif
		};

		#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0
		#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1
		#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003

		#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2
		#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2
		#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004

		#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_RX_RATE_LSB 3
		#define COEX_RX_STATUS_RX_RATE_MSB 7
		#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8

		#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_RX_BW_LSB 8
		#define COEX_RX_STATUS_RX_BW_MSB 10
		#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700

		#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11
		#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11
		#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800

		#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_FILTER_STATUS_LSB 12
		#define COEX_RX_STATUS_FILTER_STATUS_MSB 12
		#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000

		#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_AMPDU_LSB 13
		#define COEX_RX_STATUS_AMPDU_MSB 13
		#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000

		#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_DIRECTED_LSB 14
		#define COEX_RX_STATUS_DIRECTED_MSB 14
		#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000

		#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_RESERVED_0_LSB 15
		#define COEX_RX_STATUS_RESERVED_0_MSB 15
		#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000

		#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_RX_NSS_LSB 16
		#define COEX_RX_STATUS_RX_NSS_MSB 18
		#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000

		#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_RX_RSSI_LSB 19
		#define COEX_RX_STATUS_RX_RSSI_MSB 26
		#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000

		#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_RX_TYPE_LSB 27
		#define COEX_RX_STATUS_RX_TYPE_MSB 29
		#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000

		#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30
		#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30
		#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000

		#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31
		#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31
		#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000

		#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32
		#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47
		#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000

		#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000
		#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48
		#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63
		#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000

		#endif

hw/kiwi/v2/coex_tx_req.h

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hw/kiwi/v2/coex_tx_status.h

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		/*
		* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
		*
		* Permission to use, copy, modify, and/or distribute this software for any
		* purpose with or without fee is hereby granted, provided that the above
		* copyright notice and this permission notice appear in all copies.
		*
		* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
		* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
		* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
		* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
		* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
		* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
		* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
		*/



		#ifndef _COEX_TX_STATUS_H_
		#define _COEX_TX_STATUS_H_
		#if !defined(__ASSEMBLER__)
		#endif

		#define NUM_OF_DWORDS_COEX_TX_STATUS 4

		#define NUM_OF_QWORDS_COEX_TX_STATUS 2

		struct coex_tx_status {
		#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
		uint32_t reserved_0a : 7,
		tx_bw : 3,
		tx_status_reason : 3,
		tx_wait_ack : 1,
		fes_tx_is_gen_frame : 1,
		sch_tx_burst_ongoing : 1,
		current_tx_duration : 16;
		uint32_t next_rx_active_time : 16,
		remaining_fes_time : 16;
		uint32_t tx_antenna_mask : 8,
		shared_ant_tx_pwr : 8,
		other_ant_tx_pwr : 8,
		reserved_2 : 8;
		uint32_t tlv64_padding : 32;
		#else
		uint32_t current_tx_duration : 16,
		sch_tx_burst_ongoing : 1,
		fes_tx_is_gen_frame : 1,
		tx_wait_ack : 1,
		tx_status_reason : 3,
		tx_bw : 3,
		reserved_0a : 7;
		uint32_t remaining_fes_time : 16,
		next_rx_active_time : 16;
		uint32_t reserved_2 : 8,
		other_ant_tx_pwr : 8,
		shared_ant_tx_pwr : 8,
		tx_antenna_mask : 8;
		uint32_t tlv64_padding : 32;
		#endif
		};

		#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000
		#define COEX_TX_STATUS_RESERVED_0A_LSB 0
		#define COEX_TX_STATUS_RESERVED_0A_MSB 6
		#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f

		#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000
		#define COEX_TX_STATUS_TX_BW_LSB 7
		#define COEX_TX_STATUS_TX_BW_MSB 9
		#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380

		#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000
		#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10
		#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12
		#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00

		#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000
		#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13
		#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13
		#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000

		#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000
		#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14
		#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14
		#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000

		#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000
		#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15
		#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15
		#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000

		#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000
		#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16
		#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31
		#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000

		#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000
		#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32
		#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47
		#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000

		#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000
		#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48
		#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63
		#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000

		#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008
		#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0
		#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7
		#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff

		#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008
		#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8
		#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15
		#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00

		#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008
		#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16
		#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23
		#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000

		#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008
		#define COEX_TX_STATUS_RESERVED_2_LSB 24
		#define COEX_TX_STATUS_RESERVED_2_MSB 31
		#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000

		#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008
		#define COEX_TX_STATUS_TLV64_PADDING_LSB 32
		#define COEX_TX_STATUS_TLV64_PADDING_MSB 63
		#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000

		#endif

hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h

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