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Commit 08093743 authored by Neeraj Soni's avatar Neeraj Soni Committed by Blagovest Kolenichev
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mmc: cqhci: eMMC JEDEC v5.2 crypto spec addition 



Add crypto capability registers and structs defined in v5.2 of
JEDEC eMMC specification in prepration to add support for inline
encryption to eMMC controllers.

Change-Id: I8a42be348ca06cffbe841e590c4348990c9d7a08
Signed-off-by: default avatarNeeraj Soni <neersoni@codeaurora.org>
parent 4f3aa354

drivers/mmc/host/cqhci.h

+59 −0
Original line number Diff line number Diff line
@@ -31,6 +31,10 @@ 


/* capabilities */

#define CQHCI_CAP			0x04

#define CQHCI_CAP_CS			(1 << 28)

#define CQHCI_CCAP			0x100

#define CQHCI_CRYPTOCAP			0x104



/* configuration */

#define CQHCI_CFG			0x08

#define CQHCI_DCMD			0x00001000
@@ -167,6 +171,61 @@ struct cqhci_host_ops; 
struct mmc_host;

struct cqhci_slot;



/* CCAP - Crypto Capability 100h */

union cqhci_crypto_capabilities {

	__le32 reg_val;

	struct {

		u8 num_crypto_cap;

		u8 config_count;

		u8 reserved;

		u8 config_array_ptr;

	};

};



enum cqhci_crypto_key_size {

	CQHCI_CRYPTO_KEY_SIZE_INVALID	= 0x0,

	CQHCI_CRYPTO_KEY_SIZE_128	= 0x1,

	CQHCI_CRYPTO_KEY_SIZE_192	= 0x2,

	CQHCI_CRYPTO_KEY_SIZE_256	= 0x3,

	CQHCI_CRYPTO_KEY_SIZE_512	= 0x4,

};



enum cqhci_crypto_alg {

	CQHCI_CRYPTO_ALG_AES_XTS		= 0x0,

	CQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC	= 0x1,

	CQHCI_CRYPTO_ALG_AES_ECB		= 0x2,

	CQHCI_CRYPTO_ALG_ESSIV_AES_CBC		= 0x3,

};



/* x-CRYPTOCAP - Crypto Capability X */

union cqhci_crypto_cap_entry {

	__le32 reg_val;

	struct {

		u8 algorithm_id;

		u8 sdus_mask; /* Supported data unit size mask */

		u8 key_size;

		u8 reserved;

	};

};



#define CQHCI_CRYPTO_CONFIGURATION_ENABLE (1 << 7)

#define CQHCI_CRYPTO_KEY_MAX_SIZE 64

/* x-CRYPTOCFG - Crypto Configuration X */

union cqhci_crypto_cfg_entry {

	__le32 reg_val[32];

	struct {

		u8 crypto_key[CQHCI_CRYPTO_KEY_MAX_SIZE];

		u8 data_unit_size;

		u8 crypto_cap_idx;

		u8 reserved_1;

		u8 config_enable;

		u8 reserved_multi_host;

		u8 reserved_2;

		u8 vsb[2];

		u8 reserved_3[56];

	};

};



struct cqhci_host {

	const struct cqhci_host_ops *ops;

	void __iomem *mmio;