Commit 07fec1c2 authored Apr 17, 2014 by Alexander Graf

KVM: PPC: E500: Ignore L1CSR1_ICFI,ICLFR



The L1 instruction cache control register contains bits that indicate
that we're still handling a request. Mask those out when we set the SPR
so that a read doesn't assume we're still doing something.

Signed-off-by: Alexander Graf <agraf@suse.de>

parent 1f854112

arch/powerpc/kvm/e500_emulate.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -222,6 +222,7 @@ int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong spr_va
		break;
		case SPRN_L1CSR1:
		vcpu_e500->l1csr1 = spr_val;
		vcpu_e500->l1csr1 &= ~(L1CSR1_ICFI \| L1CSR1_ICLFR);
		break;
		case SPRN_HID0:
		vcpu_e500->hid0 = spr_val;