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Commit 07bdda02 authored by Michael Hennerich's avatar Michael Hennerich Committed by Bryan Wu
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Blackfin arch: bug fixing restore mach dependent ASYNC memory size 

Bug: When SMC921X driver is enabled, kernel boot crash on EZKIT548
http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3460



Fixed by restoring mach dependent ASYNC memory size CPLB coverage.
Once we have a more dynamic memory layout we should come up with a better
solution for these hard-coded values.

Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
parent 3bebca2d

include/asm-blackfin/cplb.h

+8 −2
Original line number Diff line number Diff line
@@ -65,27 +65,33 @@ 


#define MAX_CPLBS (16 * 2)



#define ASYNC_MEMORY_CPLB_COVERAGE	((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \

				 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)



/*

* Number of required data CPLB switchtable entries

* MEMSIZE / 4 (we mostly install 4M page size CPLBs

* approx 16 for smaller 1MB page size CPLBs for allignment purposes

* 1 for L1 Data Memory

* possibly 1 for L2 Data Memory

* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO

* 1 for ASYNC Memory

*/





#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)

#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \

				 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)



/*

* Number of required instruction CPLB switchtable entries

* MEMSIZE / 4 (we mostly install 4M page size CPLBs

* approx 12 for smaller 1MB page size CPLBs for allignment purposes

* 1 for L1 Instruction Memory

* possibly 1 for L2 Instruction Memory

* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO

*/



#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)

#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)





#define CPLB_ENABLE_ICACHE_P	0