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Commit 0783a560 authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
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ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks 



PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and
PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL.

Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent bad66c3e

arch/arm/mach-imx/clk-imx6sl.c

+7 −0
Original line number Diff line number Diff line
@@ -376,6 +376,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) 
	/* Audio-related clocks configuration */

	clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);



	/* set PLL5 video as lcdif pix parent clock */

	clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],

			clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);



	clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],

		       clks[IMX6SL_CLK_PLL2_PFD2]);



	/* Set initial power mode */

	imx6q_set_lpm(WAIT_CLOCKED);

}