Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 074f98df authored by Paul Mundt's avatar Paul Mundt Committed by Paul Mundt
Browse files

sh: Add 32-bit opcode feature CPU flag. 



Add a CPU flag for the CPUs that support 32-bit opcodes, which
gets passed down to userspace.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 53f983a9

arch/sh/kernel/cpu/sh2a/probe.c

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ int __init detect_cpu_and_cache_system(void) 
{

	/* Just SH7206 for now .. */

	current_cpu_data.type			= CPU_SH7206;

	current_cpu_data.flags			|= CPU_HAS_OP32;



	current_cpu_data.dcache.ways		= 4;

	current_cpu_data.dcache.way_incr	= (1 << 11);

arch/sh/kernel/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -431,7 +431,7 @@ const char *get_cpu_subtype(struct sh_cpuinfo *c) 
/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */

static const char *cpu_flags[] = {

	"none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",

	"ptea", "llsc", "l2", NULL

	"ptea", "llsc", "l2", "op32", NULL

};



static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)

include/asm-sh/cpu-features.h

+1 −0
Original line number Diff line number Diff line
@@ -20,5 +20,6 @@ 
#define CPU_HAS_PTEA		0x0020	/* PTEA register */

#define CPU_HAS_LLSC		0x0040	/* movli.l/movco.l */

#define CPU_HAS_L2_CACHE	0x0080	/* Secondary cache / URAM */

#define CPU_HAS_OP32		0x0100	/* 32-bit instruction support */



#endif /* __ASM_SH_CPU_FEATURES_H */