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Commit 071ff9a3 authored by Doug Anderson's avatar Doug Anderson Committed by Mike Turquette
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clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly 



The KDIV value is often listed as unsigned but it needs to be treated
as a 16-bit signed value when using it in calculations.  Fix our rate
recalculation to do this correctly.

Before doing this, I tried setting EPLL on exynos5250 to:
  rate, m, p, s, k = 80000000, 107, 2, 4, 43691

This rate is exactly from the table in the exynos5250 user manual.

I read this back as 80750003 with:
  cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate

After this patch, it reads back as 80000003

Signed-off-by: default avatarDoug Anderson <dianders@chromium.org>
Acked-by: default avatarKukjin Kim <kgene.kim@samsung.com>
Reviewed-by: default avatarVikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 589c603b

drivers/clk/samsung/clk-pll.c

+3 −2
Original line number Diff line number Diff line
@@ -111,7 +111,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, 
				unsigned long parent_rate)

{

	struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);

	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;

	u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;

	s16 kdiv;

	u64 fvco = parent_rate;



	pll_con0 = __raw_readl(pll->con_reg);
@@ -119,7 +120,7 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, 
	mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;

	pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;

	sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;

	kdiv = pll_con1 & PLL36XX_KDIV_MASK;

	kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);



	fvco *= (mdiv << 16) + kdiv;

	do_div(fvco, (pdiv << sdiv));