Merge tag 'gvt-next-2016-10-14' of https://github.com/01org/gvt-linux into drm-intel-next-queued

GVT_DIR := gvt

GVT_SOURCE := gvt.o

GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \

	interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \

	execlist.o scheduler.o sched_policy.o render.o cmd_parser.o

ccflags-y                      += -I$(src) -I$(src)/$(GVT_DIR) -Wall

i915-y			       += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))

/*

 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

 * SOFTWARE.

 *

 * Authors:

 *    Kevin Tian <kevin.tian@intel.com>

 *    Dexuan Cui

 *

 * Contributors:

 *    Pei Zhang <pei.zhang@intel.com>

 *    Min He <min.he@intel.com>

 *    Niu Bing <bing.niu@intel.com>

 *    Yulei Zhang <yulei.zhang@intel.com>

 *    Zhenyu Wang <zhenyuw@linux.intel.com>

 *    Zhi Wang <zhi.a.wang@intel.com>

 *

 */

#include "i915_drv.h"

#define MB_TO_BYTES(mb) ((mb) << 20ULL)

#define BYTES_TO_MB(b) ((b) >> 20ULL)

#define HOST_LOW_GM_SIZE MB_TO_BYTES(128)

#define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)

#define HOST_FENCE 4

static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)

{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	u32 alloc_flag, search_flag;

	u64 start, end, size;

	struct drm_mm_node *node;

	int retried = 0;

	int ret;

	if (high_gm) {

		search_flag = DRM_MM_SEARCH_BELOW;

		alloc_flag = DRM_MM_CREATE_TOP;

		node = &vgpu->gm.high_gm_node;

		size = vgpu_hidden_sz(vgpu);

		start = gvt_hidden_gmadr_base(gvt);

		end = gvt_hidden_gmadr_end(gvt);

	} else {

		search_flag = DRM_MM_SEARCH_DEFAULT;

		alloc_flag = DRM_MM_CREATE_DEFAULT;

		node = &vgpu->gm.low_gm_node;

		size = vgpu_aperture_sz(vgpu);

		start = gvt_aperture_gmadr_base(gvt);

		end = gvt_aperture_gmadr_end(gvt);

	}

	mutex_lock(&dev_priv->drm.struct_mutex);

search_again:

	ret = drm_mm_insert_node_in_range_generic(&dev_priv->ggtt.base.mm,

						  node, size, 4096, 0,

						  start, end, search_flag,

						  alloc_flag);

	if (ret) {

		ret = i915_gem_evict_something(&dev_priv->ggtt.base,

					       size, 4096, 0, start, end, 0);

		if (ret == 0 && ++retried < 3)

			goto search_again;

		gvt_err("fail to alloc %s gm space from host, retried %d\n",

				high_gm ? "high" : "low", retried);

	}

	mutex_unlock(&dev_priv->drm.struct_mutex);

	return ret;

}

static int alloc_vgpu_gm(struct intel_vgpu *vgpu)

{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	int ret;

	ret = alloc_gm(vgpu, false);

	if (ret)

		return ret;

	ret = alloc_gm(vgpu, true);

	if (ret)

		goto out_free_aperture;

	gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id,

		     vgpu_aperture_offset(vgpu), vgpu_aperture_sz(vgpu));

	gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id,

		     vgpu_hidden_offset(vgpu), vgpu_hidden_sz(vgpu));

	return 0;

out_free_aperture:

	mutex_lock(&dev_priv->drm.struct_mutex);

	drm_mm_remove_node(&vgpu->gm.low_gm_node);

	mutex_unlock(&dev_priv->drm.struct_mutex);

	return ret;

}

static void free_vgpu_gm(struct intel_vgpu *vgpu)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	mutex_lock(&dev_priv->drm.struct_mutex);

	drm_mm_remove_node(&vgpu->gm.low_gm_node);

	drm_mm_remove_node(&vgpu->gm.high_gm_node);

	mutex_unlock(&dev_priv->drm.struct_mutex);

}

/**

 * intel_vgpu_write_fence - write fence registers owned by a vGPU

 * @vgpu: vGPU instance

 * @fence: vGPU fence register number

 * @value: Fence register value to be written

 *

 * This function is used to write fence registers owned by a vGPU. The vGPU

 * fence register number will be translated into HW fence register number.

 *

 */

void intel_vgpu_write_fence(struct intel_vgpu *vgpu,

		u32 fence, u64 value)

{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct drm_i915_fence_reg *reg;

	i915_reg_t fence_reg_lo, fence_reg_hi;

	if (WARN_ON(fence > vgpu_fence_sz(vgpu)))

		return;

	reg = vgpu->fence.regs[fence];

	if (WARN_ON(!reg))

		return;

	fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);

	fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);

	I915_WRITE(fence_reg_lo, 0);

	POSTING_READ(fence_reg_lo);

	I915_WRITE(fence_reg_hi, upper_32_bits(value));

	I915_WRITE(fence_reg_lo, lower_32_bits(value));

	POSTING_READ(fence_reg_lo);

}

static void free_vgpu_fence(struct intel_vgpu *vgpu)

{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct drm_i915_fence_reg *reg;

	u32 i;

	if (WARN_ON(!vgpu_fence_sz(vgpu)))

		return;

	mutex_lock(&dev_priv->drm.struct_mutex);

	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {

		reg = vgpu->fence.regs[i];

		intel_vgpu_write_fence(vgpu, i, 0);

		list_add_tail(&reg->link,

			      &dev_priv->mm.fence_list);

	}

	mutex_unlock(&dev_priv->drm.struct_mutex);

}

static int alloc_vgpu_fence(struct intel_vgpu *vgpu)

{

	struct intel_gvt *gvt = vgpu->gvt;

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct drm_i915_fence_reg *reg;

	int i;

	struct list_head *pos, *q;

	/* Request fences from host */

	mutex_lock(&dev_priv->drm.struct_mutex);

	i = 0;

	list_for_each_safe(pos, q, &dev_priv->mm.fence_list) {

		reg = list_entry(pos, struct drm_i915_fence_reg, link);

		if (reg->pin_count || reg->vma)

			continue;

		list_del(pos);

		vgpu->fence.regs[i] = reg;

		intel_vgpu_write_fence(vgpu, i, 0);

		if (++i == vgpu_fence_sz(vgpu))

			break;

	}

	if (i != vgpu_fence_sz(vgpu))

		goto out_free_fence;

	mutex_unlock(&dev_priv->drm.struct_mutex);

	return 0;

out_free_fence:

	/* Return fences to host, if fail */

	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {

		reg = vgpu->fence.regs[i];

		if (!reg)

			continue;

		list_add_tail(&reg->link,

			      &dev_priv->mm.fence_list);

	}

	mutex_unlock(&dev_priv->drm.struct_mutex);

	return -ENOSPC;

}

static void free_resource(struct intel_vgpu *vgpu)

{

	struct intel_gvt *gvt = vgpu->gvt;

	gvt->gm.vgpu_allocated_low_gm_size -= vgpu_aperture_sz(vgpu);

	gvt->gm.vgpu_allocated_high_gm_size -= vgpu_hidden_sz(vgpu);

	gvt->fence.vgpu_allocated_fence_num -= vgpu_fence_sz(vgpu);

}

static int alloc_resource(struct intel_vgpu *vgpu,

		struct intel_vgpu_creation_params *param)

{

	struct intel_gvt *gvt = vgpu->gvt;

	unsigned long request, avail, max, taken;

	const char *item;

	if (!param->low_gm_sz || !param->high_gm_sz || !param->fence_sz) {

		gvt_err("Invalid vGPU creation params\n");

		return -EINVAL;

	}

	item = "low GM space";

	max = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;

	taken = gvt->gm.vgpu_allocated_low_gm_size;

	avail = max - taken;

	request = MB_TO_BYTES(param->low_gm_sz);

	if (request > avail)

		goto no_enough_resource;

	vgpu_aperture_sz(vgpu) = request;

	item = "high GM space";

	max = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;

	taken = gvt->gm.vgpu_allocated_high_gm_size;

	avail = max - taken;

	request = MB_TO_BYTES(param->high_gm_sz);

	if (request > avail)

		goto no_enough_resource;

	vgpu_hidden_sz(vgpu) = request;

	item = "fence";

	max = gvt_fence_sz(gvt) - HOST_FENCE;

	taken = gvt->fence.vgpu_allocated_fence_num;

	avail = max - taken;

	request = param->fence_sz;

	if (request > avail)

		goto no_enough_resource;

	vgpu_fence_sz(vgpu) = request;

	gvt->gm.vgpu_allocated_low_gm_size += MB_TO_BYTES(param->low_gm_sz);

	gvt->gm.vgpu_allocated_high_gm_size += MB_TO_BYTES(param->high_gm_sz);

	gvt->fence.vgpu_allocated_fence_num += param->fence_sz;

	return 0;

no_enough_resource:

	gvt_err("vgpu%d: fail to allocate resource %s\n", vgpu->id, item);

	gvt_err("vgpu%d: request %luMB avail %luMB max %luMB taken %luMB\n",

		vgpu->id, BYTES_TO_MB(request), BYTES_TO_MB(avail),

		BYTES_TO_MB(max), BYTES_TO_MB(taken));

	return -ENOSPC;

}

/**

 * inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU

 * @vgpu: a vGPU

 *

 * This function is used to free the HW resource owned by a vGPU.

 *

 */

void intel_vgpu_free_resource(struct intel_vgpu *vgpu)

{

	free_vgpu_gm(vgpu);

	free_vgpu_fence(vgpu);

	free_resource(vgpu);

}

/**

 * intel_alloc_vgpu_resource - allocate HW resource for a vGPU

 * @vgpu: vGPU

 * @param: vGPU creation params

 *

 * This function is used to allocate HW resource for a vGPU. User specifies

 * the resource configuration through the creation params.

 *

 * Returns:

 * zero on success, negative error code if failed.

 *

 */

int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,

		struct intel_vgpu_creation_params *param)

{

	int ret;

	ret = alloc_resource(vgpu, param);

	if (ret)

		return ret;

	ret = alloc_vgpu_gm(vgpu);

	if (ret)

		goto out_free_resource;

	ret = alloc_vgpu_fence(vgpu);

	if (ret)

		goto out_free_vgpu_gm;

	return 0;

out_free_vgpu_gm:

	free_vgpu_gm(vgpu);

out_free_resource:

	free_resource(vgpu);

	return ret;

}

/*

 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

 * SOFTWARE.

 *

 * Authors:

 *    Eddie Dong <eddie.dong@intel.com>

 *    Jike Song <jike.song@intel.com>

 *

 * Contributors:

 *    Zhi Wang <zhi.a.wang@intel.com>

 *    Min He <min.he@intel.com>

 *    Bing Niu <bing.niu@intel.com>

 *

 */

#include "i915_drv.h"

enum {

	INTEL_GVT_PCI_BAR_GTTMMIO = 0,

	INTEL_GVT_PCI_BAR_APERTURE,

	INTEL_GVT_PCI_BAR_PIO,

	INTEL_GVT_PCI_BAR_MAX,

};

/**

 * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read

 *

 * Returns:

 * Zero on success, negative error code if failed.

 */

int intel_vgpu_emulate_cfg_read(void *__vgpu, unsigned int offset,

	void *p_data, unsigned int bytes)

{

	struct intel_vgpu *vgpu = __vgpu;

	if (WARN_ON(bytes > 4))

		return -EINVAL;

	if (WARN_ON(offset + bytes > INTEL_GVT_MAX_CFG_SPACE_SZ))

		return -EINVAL;

	memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);

	return 0;

}

static int map_aperture(struct intel_vgpu *vgpu, bool map)

{

	u64 first_gfn, first_mfn;

	u64 val;

	int ret;

	if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)

		return 0;

	val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2];

	if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)

		val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);

	else

		val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);

	first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT;

	first_mfn = vgpu_aperture_pa_base(vgpu) >> PAGE_SHIFT;

	ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn,

						  first_mfn,

						  vgpu_aperture_sz(vgpu)

						  >> PAGE_SHIFT, map,

						  GVT_MAP_APERTURE);

	if (ret)

		return ret;

	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;

	return 0;

}

static int trap_gttmmio(struct intel_vgpu *vgpu, bool trap)

{

	u64 start, end;

	u64 val;

	int ret;

	if (trap == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked)

		return 0;

	val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0];

	if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)

		start = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);

	else

		start = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);

	start &= ~GENMASK(3, 0);

	end = start + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size - 1;

	ret = intel_gvt_hypervisor_set_trap_area(vgpu, start, end, trap);

	if (ret)

		return ret;

	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap;

	return 0;

}

static int emulate_pci_command_write(struct intel_vgpu *vgpu,

	unsigned int offset, void *p_data, unsigned int bytes)

{

	u8 old = vgpu_cfg_space(vgpu)[offset];

	u8 new = *(u8 *)p_data;

	u8 changed = old ^ new;

	int ret;

	if (!(changed & PCI_COMMAND_MEMORY))

		return 0;

	if (old & PCI_COMMAND_MEMORY) {

		ret = trap_gttmmio(vgpu, false);

		if (ret)

			return ret;

		ret = map_aperture(vgpu, false);

		if (ret)

			return ret;

	} else {

		ret = trap_gttmmio(vgpu, true);

		if (ret)

			return ret;

		ret = map_aperture(vgpu, true);

		if (ret)

			return ret;

	}

	memcpy(vgpu_cfg_space(vgpu) + offset, p_data, bytes);

	return 0;

}

static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,

	void *p_data, unsigned int bytes)

{

	unsigned int bar_index =

		(rounddown(offset, 8) % PCI_BASE_ADDRESS_0) / 8;

	u32 new = *(u32 *)(p_data);

	bool lo = IS_ALIGNED(offset, 8);

	u64 size;

	int ret = 0;

	bool mmio_enabled =

		vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;

	if (WARN_ON(bar_index >= INTEL_GVT_PCI_BAR_MAX))

		return -EINVAL;

	if (new == 0xffffffff) {

		/*

		 * Power-up software can determine how much address

		 * space the device requires by writing a value of

		 * all 1's to the register and then reading the value

		 * back. The device will return 0's in all don't-care

		 * address bits.

		 */

		size = vgpu->cfg_space.bar[bar_index].size;

		if (lo) {

			new = rounddown(new, size);

		} else {

			u32 val = vgpu_cfg_space(vgpu)[rounddown(offset, 8)];

			/* for 32bit mode bar it returns all-0 in upper 32

			 * bit, for 64bit mode bar it will calculate the

			 * size with lower 32bit and return the corresponding

			 * value

			 */

			if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)

				new &= (~(size-1)) >> 32;

			else

				new = 0;

		}

		/*

		 * Unmapp & untrap the BAR, since guest hasn't configured a

		 * valid GPA

		 */

		switch (bar_index) {

		case INTEL_GVT_PCI_BAR_GTTMMIO:

			ret = trap_gttmmio(vgpu, false);

			break;

		case INTEL_GVT_PCI_BAR_APERTURE:

			ret = map_aperture(vgpu, false);

			break;

		}

		intel_vgpu_write_pci_bar(vgpu, offset, new, lo);

	} else {

		/*

		 * Unmapp & untrap the old BAR first, since guest has

		 * re-configured the BAR

		 */

		switch (bar_index) {

		case INTEL_GVT_PCI_BAR_GTTMMIO:

			ret = trap_gttmmio(vgpu, false);

			break;

		case INTEL_GVT_PCI_BAR_APERTURE:

			ret = map_aperture(vgpu, false);

			break;

		}

		intel_vgpu_write_pci_bar(vgpu, offset, new, lo);

		/* Track the new BAR */

		if (mmio_enabled) {

			switch (bar_index) {

			case INTEL_GVT_PCI_BAR_GTTMMIO:

				ret = trap_gttmmio(vgpu, true);

				break;

			case INTEL_GVT_PCI_BAR_APERTURE:

				ret = map_aperture(vgpu, true);

				break;

			}

		}

	}

	return ret;

}

/**

 * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write

 *

 * Returns:

 * Zero on success, negative error code if failed.

 */

int intel_vgpu_emulate_cfg_write(void *__vgpu, unsigned int offset,

	void *p_data, unsigned int bytes)

{

	struct intel_vgpu *vgpu = __vgpu;

	int ret;

	if (WARN_ON(bytes > 4))

		return -EINVAL;

	if (WARN_ON(offset + bytes >= INTEL_GVT_MAX_CFG_SPACE_SZ))

		return -EINVAL;

	/* First check if it's PCI_COMMAND */

	if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) {

		if (WARN_ON(bytes > 2))

			return -EINVAL;

		return emulate_pci_command_write(vgpu, offset, p_data, bytes);

	}

	switch (rounddown(offset, 4)) {

	case PCI_BASE_ADDRESS_0:

	case PCI_BASE_ADDRESS_1:

	case PCI_BASE_ADDRESS_2:

	case PCI_BASE_ADDRESS_3:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

			return -EINVAL;

		return emulate_pci_bar_write(vgpu, offset, p_data, bytes);

	case INTEL_GVT_PCI_SWSCI:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

			return -EINVAL;

		ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);

		if (ret)

			return ret;

		break;

	case INTEL_GVT_PCI_OPREGION:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

			return -EINVAL;

		ret = intel_vgpu_init_opregion(vgpu, *(u32 *)p_data);

		if (ret)

			return ret;

		memcpy(vgpu_cfg_space(vgpu) + offset, p_data, bytes);

		break;

	default:

		memcpy(vgpu_cfg_space(vgpu) + offset, p_data, bytes);

		break;

	}

	return 0;

}