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Commit 064e6a8b authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'linus' into x86/fpu, to resolve conflicts 



 Conflicts:
	arch/x86/kernel/fpu/core.c

Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents af25ed59 23400ac9

Documentation/ABI/testing/sysfs-devices-system-ibm-rtl

+2 −2
Original line number Diff line number Diff line 
What:           state

What:           /sys/devices/system/ibm_rtl/state

Date:           Sep 2010

KernelVersion:  2.6.37

Contact:        Vernon Mauery <vernux@us.ibm.com>
@@ -10,7 +10,7 @@ Description: The state file allows a means by which to change in and 
Users:          The ibm-prtm userspace daemon uses this interface.





What:           version

What:           /sys/devices/system/ibm_rtl/version

Date:           Sep 2010

KernelVersion:  2.6.37

Contact:        Vernon Mauery <vernux@us.ibm.com>

Documentation/devicetree/bindings/ipmi/aspeed,ast2400-bt-bmc.txt→Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt

+2 −2
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ perform in-band IPMI communication with their host. 


Required properties:



- compatible : should be "aspeed,ast2400-bt-bmc"

- compatible : should be "aspeed,ast2400-ibt-bmc"

- reg: physical address and size of the registers



Optional properties:
@@ -17,7 +17,7 @@ Optional properties: 
Example:



	ibt@1e789140 {

		compatible = "aspeed,ast2400-bt-bmc";

		compatible = "aspeed,ast2400-ibt-bmc";

		reg = <0x1e789140 0x18>;

		interrupts = <8>;

	};

Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt

+5 −0
Original line number Diff line number Diff line
@@ -43,6 +43,9 @@ Optional properties: 
  reset signal present internally in some host controller IC designs.

  See Documentation/devicetree/bindings/reset/reset.txt for details.



* reset-names: request name for using "resets" property. Must be "reset".

	(It will be used together with "resets" property.)



* clocks: from common clock binding: handle to biu and ciu clocks for the

  bus interface unit clock and the card interface unit clock.
@@ -103,6 +106,8 @@ board specific portions as listed below. 
		interrupts = <0 75 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		resets = <&rst 20>;

		reset-names = "reset";

	};



[board specific internal DMA resources]

Documentation/devicetree/bindings/pci/rockchip-pcie.txt

+8 −3
Original line number Diff line number Diff line
@@ -26,13 +26,16 @@ Required properties: 
	- "sys"

	- "legacy"

	- "client"

- resets: Must contain five entries for each entry in reset-names.

- resets: Must contain seven entries for each entry in reset-names.

	   See ../reset/reset.txt for details.

- reset-names: Must include the following names

	- "core"

	- "mgmt"

	- "mgmt-sticky"

	- "pipe"

	- "pm"

	- "aclk"

	- "pclk"

- pinctrl-names : The pin control state names

- pinctrl-0: The "default" pinctrl state

- #interrupt-cells: specifies the number of cells needed to encode an
@@ -86,8 +89,10 @@ pcie0: pcie@f8000000 { 
	reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;

	reg-names = "axi-base", "apb-base";

	resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,

		 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;

	reset-names = "core", "mgmt", "mgmt-sticky", "pipe";

		 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,

		 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;

	reset-names = "core", "mgmt", "mgmt-sticky", "pipe",

		      "pm", "pclk", "aclk";

	phys = <&pcie_phy>;

	phy-names = "pcie-phy";

	pinctrl-names = "default";

Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt

+5 −5
Original line number Diff line number Diff line
@@ -14,11 +14,6 @@ Required properies: 
 - #size-cells	: The value of this property must be 1

 - ranges	: defines mapping between pin controller node (parent) to

   gpio-bank node (children).

 - interrupt-parent: phandle of the interrupt parent to which the external

   GPIO interrupts are forwarded to.

 - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node

   which includes IRQ mux selection register, and the offset of the IRQ mux

   selection register.

 - pins-are-numbered: Specify the subnodes are using numbered pinmux to

   specify pins.
@@ -37,6 +32,11 @@ Required properties: 


Optional properties:

 - reset:	  : Reference to the reset controller

 - interrupt-parent: phandle of the interrupt parent to which the external

   GPIO interrupts are forwarded to.

 - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node

   which includes IRQ mux selection register, and the offset of the IRQ mux

   selection register.



Example:

#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>