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Commit 06482600 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Catalin Marinas:

 - SPsel register initialisation on reset as the architecture defines
   its state as unknown

 - Use READ_ONCE when dereferencing pmd_t pointers to avoid race
   conditions in page_vma_mapped_walk() (or fast GUP) with concurrent
   modifications of the page table

 - Avoid invoking the mm fault handling code for kernel addresses (check
   against TASK_SIZE) which would otherwise result in calling
   might_sleep() in atomic context

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: fault: Route pte translation faults via do_translation_fault
  arm64: mm: Use READ_ONCE when dereferencing pointer to pte table
  arm64: Make sure SPsel is always set
parents 9f2a5128 760bfb47

arch/arm64/include/asm/pgtable.h

+1 −1
Original line number Diff line number Diff line
@@ -401,7 +401,7 @@ static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 
/* Find an entry in the third-level page table. */

#define pte_index(addr)		(((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))



#define pte_offset_phys(dir,addr)	(pmd_page_paddr(*(dir)) + pte_index(addr) * sizeof(pte_t))

#define pte_offset_phys(dir,addr)	(pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))

#define pte_offset_kernel(dir,addr)	((pte_t *)__va(pte_offset_phys((dir), (addr))))



#define pte_offset_map(dir,addr)	pte_offset_kernel((dir), (addr))

arch/arm64/kernel/head.S

+1 −0
Original line number Diff line number Diff line
@@ -384,6 +384,7 @@ ENTRY(kimage_vaddr) 
 * booted in EL1 or EL2 respectively.

 */

ENTRY(el2_setup)

	msr	SPsel, #1			// We want to use SP_EL{1,2}

	mrs	x0, CurrentEL

	cmp	x0, #CurrentEL_EL2

	b.eq	1f

arch/arm64/mm/fault.c

+1 −1
Original line number Diff line number Diff line
@@ -651,7 +651,7 @@ static const struct fault_info fault_info[] = { 
	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"level 0 translation fault"	},

	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"level 1 translation fault"	},

	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"level 2 translation fault"	},

	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"level 3 translation fault"	},

	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"level 3 translation fault"	},

	{ do_bad,		SIGBUS,  0,		"unknown 8"			},

	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 1 access flag fault"	},

	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 access flag fault"	},