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Commit 05b1c588 authored by Harshdeep Dhatt's avatar Harshdeep Dhatt Committed by Harshitha Sai Neelati
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msm: kgsl: Remove dev_err() from fenced write loop



dev_err() can take milliseconds to finish which can allow
GMU to come out of IFPC and go back to IFPC before kgsl gets
a chance to update the fenced register.

Change-Id: Ic1846188213da571c23d52b8a78eb2162a8adc7b
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
Signed-off-by: default avatarHarshitha Sai Neelati <hsaine@codeaurora.org>
parent 32735954
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+18 −13
Original line number Diff line number Diff line
@@ -3411,31 +3411,36 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,
		 * was successful
		 */
		if (!(status & fence_mask))
			return 0;
			break;

		/* Wait a small amount of time before trying again */
		udelay(GMU_CORE_WAKEUP_DELAY_US);

		/* Try to write the fenced register again */
		adreno_writereg(adreno_dev, offset, val);

		if (i == GMU_CORE_SHORT_WAKEUP_RETRY_LIMIT)
			dev_err(device->dev,
				"Waited %d usecs to write fenced register 0x%x, status 0x%x. Continuing to wait...\n",
				(GMU_CORE_SHORT_WAKEUP_RETRY_LIMIT *
				GMU_CORE_WAKEUP_DELAY_US),
				reg_offset, status);
	}

	if (i < GMU_CORE_SHORT_WAKEUP_RETRY_LIMIT)
		return 0;

	ts2 = gmu_core_dev_read_ao_counter(device);

	if (i == GMU_CORE_LONG_WAKEUP_RETRY_LIMIT) {
		dev_err(device->dev,
		"fenced write for 0x%x timed out in %dus. timestamps %llu %llu, status 0x%x\n",
		reg_offset,
		GMU_CORE_LONG_WAKEUP_RETRY_LIMIT * GMU_CORE_WAKEUP_DELAY_US,
		ts1, ts2, status);
			"Timed out waiting %d usecs to write fenced register 0x%x, timestamps %llu %llu, status 0x%x\n",
			i * GMU_CORE_WAKEUP_DELAY_US,
			reg_offset, ts1, ts2, status);

		return -ETIMEDOUT;
	}

	dev_err(device->dev,
		"Waited %d usecs to write fenced register 0x%x. status 0x%x\n",
		i * GMU_CORE_WAKEUP_DELAY_US, reg_offset, status);

	return 0;
}

bool adreno_is_cx_dbgc_register(struct kgsl_device *device,
		unsigned int offsetwords)
{