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Commit 056db9d7 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-4.14-3' of... 

Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull more Allwinner clock changes from Maxime Ripard:

 * Conversion of the last two SoCs (A10, A20) to the sunxi-ng framework

* tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: Add sun4i/sun7i CCU driver
  dt-bindings: List devicetree binding for the CCU of Allwinner A10
  dt-bindings: List devicetree binding for the CCU of Allwinner A20
parents 4e903450 c84f5683

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

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@@ -3,9 +3,11 @@ Allwinner Clock Control Unit Binding 


Required properties :

- compatible: must contain one of the following compatibles:

		- "allwinner,sun4i-a10-ccu"

		- "allwinner,sun5i-a10s-ccu"

		- "allwinner,sun5i-a13-ccu"

		- "allwinner,sun6i-a31-ccu"

		- "allwinner,sun7i-a20-ccu"

		- "allwinner,sun8i-a23-ccu"

		- "allwinner,sun8i-a33-ccu"

		- "allwinner,sun8i-a83t-ccu"

drivers/clk/sunxi-ng/Kconfig

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@@ -11,6 +11,19 @@ config SUN50I_A64_CCU 
	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST



config SUN4I_A10_CCU

	bool "Support for the Allwinner A10/A20 CCU"

	select SUNXI_CCU_DIV

	select SUNXI_CCU_MULT

	select SUNXI_CCU_NK

	select SUNXI_CCU_NKM

	select SUNXI_CCU_NM

	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	default MACH_SUN4I

	default MACH_SUN7I

	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST



config SUN5I_CCU

	bool "Support for the Allwinner sun5i family CCM"

	default MACH_SUN5I

drivers/clk/sunxi-ng/Makefile

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@@ -19,6 +19,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_mp.o 


# SoC support

obj-$(CONFIG_SUN50I_A64_CCU)	+= ccu-sun50i-a64.o

obj-$(CONFIG_SUN4I_A10_CCU)	+= ccu-sun4i-a10.o

obj-$(CONFIG_SUN5I_CCU)		+= ccu-sun5i.o

obj-$(CONFIG_SUN6I_A31_CCU)	+= ccu-sun6i-a31.o

obj-$(CONFIG_SUN8I_A23_CCU)	+= ccu-sun8i-a23.o

drivers/clk/sunxi-ng/ccu-sun4i-a10.c

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drivers/clk/sunxi-ng/ccu-sun4i-a10.h

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/*

 * Copyright 2017 Priit Laes

 *

 * Priit Laes <plaes@plaes.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _CCU_SUN4I_A10_H_

#define _CCU_SUN4I_A10_H_



#include <dt-bindings/clock/sun4i-a10-ccu.h>

#include <dt-bindings/clock/sun7i-a20-ccu.h>

#include <dt-bindings/reset/sun4i-a10-ccu.h>



/* The HOSC is exported */

#define CLK_PLL_CORE		2

#define CLK_PLL_AUDIO_BASE	3

#define CLK_PLL_AUDIO		4

#define CLK_PLL_AUDIO_2X	5

#define CLK_PLL_AUDIO_4X	6

#define CLK_PLL_AUDIO_8X	7

#define CLK_PLL_VIDEO0		8

#define CLK_PLL_VIDEO0_2X	9

#define CLK_PLL_VE		10

#define CLK_PLL_DDR_BASE	11

#define CLK_PLL_DDR		12

#define CLK_PLL_DDR_OTHER	13

#define CLK_PLL_PERIPH_BASE	14

#define CLK_PLL_PERIPH		15

#define CLK_PLL_PERIPH_SATA	16

#define CLK_PLL_VIDEO1		17

#define CLK_PLL_VIDEO1_2X	18

#define CLK_PLL_GPU		19



/* The CPU clock is exported */

#define CLK_AXI			21

#define CLK_AXI_DRAM		22

#define CLK_AHB			23

#define CLK_APB0		24

#define CLK_APB1		25



/* AHB gates are exported (23..68) */

/* APB0 gates are exported (69..78) */

/* APB1 gates are exported (79..95) */

/* IP module clocks are exported (96..128) */

/* DRAM gates are exported (129..142)*/

/* Media (display engine clocks & etc) are exported (143..169) */



#define CLK_NUMBER_SUN4I	(CLK_MBUS + 1)

#define CLK_NUMBER_SUN7I	(CLK_OUT_B + 1)



#endif /* _CCU_SUN4I_A10_H_ */