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Commit 0565fb16 authored by Tero Kristo's avatar Tero Kristo
Browse files

clk: ti: dpll: move omap3 DPLL functionality to clock driver 



With the legacy clock support gone, OMAP3 generic DPLL code can now be
moved over to the clock driver also. A few un-unused clkoutx2 functions
are also removed at the same time.

Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent 192383d8

arch/arm/mach-omap2/Makefile

+2 −6
Original line number Diff line number Diff line
@@ -189,15 +189,11 @@ obj-$(CONFIG_SOC_OMAP2430) += clock2430.o 
obj-$(CONFIG_ARCH_OMAP3)		+= $(clock-common) clock3xxx.o

obj-$(CONFIG_ARCH_OMAP3)		+= clock34xx.o clkt34xx_dpll3m2.o

obj-$(CONFIG_ARCH_OMAP3)		+= clock3517.o

obj-$(CONFIG_ARCH_OMAP3)		+= dpll3xxx.o

obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common)

obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o

obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o

obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common)

obj-$(CONFIG_SOC_OMAP5)			+= $(clock-common)

obj-$(CONFIG_SOC_OMAP5)			+= dpll3xxx.o

obj-$(CONFIG_SOC_DRA7XX)		+= $(clock-common)

obj-$(CONFIG_SOC_DRA7XX)		+= dpll3xxx.o

obj-$(CONFIG_SOC_AM43XX)		+= $(clock-common) dpll3xxx.o

obj-$(CONFIG_SOC_AM43XX)		+= $(clock-common)



# OMAP2 clock rate set data (old "OPP" data)

obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o

arch/arm/mach-omap2/clock.h

+0 −4
Original line number Diff line number Diff line
@@ -180,10 +180,6 @@ struct clksel { 
#define OMAP4XXX_EN_DPLL_FRBYPASS		0x6

#define OMAP4XXX_EN_DPLL_LOCKED			0x7



u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);

void omap3_dpll_allow_idle(struct clk_hw_omap *clk);

void omap3_dpll_deny_idle(struct clk_hw_omap *clk);



void __init omap2_clk_disable_clkdm_control(void);



void omap2_clk_print_new_rates(const char *hfclkin_ck_name,

arch/arm/mach-omap2/clock3xxx.c

+0 −77
Original line number Diff line number Diff line
@@ -29,82 +29,5 @@ 
#include "cm2xxx_3xxx.h"

#include "cm-regbits-34xx.h"



/*

 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks

 * that are sourced by DPLL5, and both of these require this clock

 * to be at 120 MHz for proper operation.

 */

#define DPLL5_FREQ_FOR_USBHOST		120000000



/* needed by omap3_core_dpll_m2_set_rate() */

struct clk *sdrc_ick_p, *arm_fck_p;
 


/**

 * omap3_dpll4_set_rate - set rate for omap3 per-dpll

 * @hw: clock to change

 * @rate: target rate for clock

 * @parent_rate: rate of the parent clock

 *

 * Check if the current SoC supports the per-dpll reprogram operation

 * or not, and then do the rate change if supported. Returns -EINVAL

 * if not supported, 0 for success, and potential error codes from the

 * clock rate change.

 */

int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,

				unsigned long parent_rate)

{

	/*

	 * According to the 12-5 CDP code from TI, "Limitation 2.5"

	 * on 3430ES1 prevents us from changing DPLL multipliers or dividers

	 * on DPLL4.

	 */

	if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {

		pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");

		return -EINVAL;

	}



	return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);

}



/**

 * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll

 * @hw: clock to change

 * @rate: target rate for clock

 * @parent_rate: rate of the parent clock

 * @index: parent index, 0 - reference clock, 1 - bypass clock

 *

 * Check if the current SoC support the per-dpll reprogram operation

 * or not, and then do the rate + parent change if supported. Returns

 * -EINVAL if not supported, 0 for success, and potential error codes

 * from the clock rate change.

 */

int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,

				    unsigned long parent_rate, u8 index)

{

	if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {

		pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");

		return -EINVAL;

	}



	return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,

						      index);

}



void __init omap3_clk_lock_dpll5(void)

{

	struct clk *dpll5_clk;

	struct clk *dpll5_m2_clk;



	dpll5_clk = clk_get(NULL, "dpll5_ck");

	clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);

	clk_prepare_enable(dpll5_clk);



	/* Program dpll5_m2_clk divider for no division */

	dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");

	clk_prepare_enable(dpll5_m2_clk);

	clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);



	clk_disable_unprepare(dpll5_m2_clk);

	clk_disable_unprepare(dpll5_clk);

	return;

}

drivers/clk/ti/Makefile

+8 −6
Original line number Diff line number Diff line
@@ -2,16 +2,18 @@ obj-y += clk.o autoidle.o clockdomain.o 
clk-common				= dpll.o composite.o divider.o gate.o \

					  fixed-factor.o mux.o apll.o \

					  clkt_dpll.o clkt_iclk.o

obj-$(CONFIG_SOC_AM33XX)		+= $(clk-common) clk-33xx.o

obj-$(CONFIG_SOC_AM33XX)		+= $(clk-common) clk-33xx.o dpll3xxx.o

obj-$(CONFIG_SOC_TI81XX)		+= $(clk-common) fapll.o clk-816x.o

obj-$(CONFIG_ARCH_OMAP2)		+= $(clk-common) interface.o clk-2xxx.o

obj-$(CONFIG_ARCH_OMAP3)		+= $(clk-common) interface.o \

					   clk-3xxx.o

obj-$(CONFIG_ARCH_OMAP4)		+= $(clk-common) clk-44xx.o dpll44xx.o

obj-$(CONFIG_SOC_OMAP5)			+= $(clk-common) clk-54xx.o dpll44xx.o

					   clk-3xxx.o dpll3xxx.o

obj-$(CONFIG_ARCH_OMAP4)		+= $(clk-common) clk-44xx.o \

					   dpll3xxx.o dpll44xx.o

obj-$(CONFIG_SOC_OMAP5)			+= $(clk-common) clk-54xx.o \

					   dpll3xxx.o dpll44xx.o

obj-$(CONFIG_SOC_DRA7XX)		+= $(clk-common) clk-7xx.o \

					   clk-dra7-atl.o dpll44xx.o

obj-$(CONFIG_SOC_AM43XX)		+= $(clk-common) clk-43xx.o

					   clk-dra7-atl.o dpll3xxx.o dpll44xx.o

obj-$(CONFIG_SOC_AM43XX)		+= $(clk-common) dpll3xxx.o clk-43xx.o



ifdef CONFIG_ATAGS

obj-$(CONFIG_ARCH_OMAP3)                += clk-3xxx-legacy.o

drivers/clk/ti/clk-3xxx.c

+31 −0
Original line number Diff line number Diff line
@@ -21,6 +21,13 @@ 


#include "clock.h"



/*

 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks

 * that are sourced by DPLL5, and both of these require this clock

 * to be at 120 MHz for proper operation.

 */

#define DPLL5_FREQ_FOR_USBHOST		120000000



static struct ti_dt_clk omap3xxx_clks[] = {

	DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),

	DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
@@ -325,6 +332,30 @@ enum { 
	OMAP3_SOC_OMAP3630,

};



/**

 * omap3_clk_lock_dpll5 - locks DPLL5

 *

 * Locks DPLL5 to a pre-defined frequency. This is required for proper

 * operation of USB.

 */

void __init omap3_clk_lock_dpll5(void)

{

	struct clk *dpll5_clk;

	struct clk *dpll5_m2_clk;



	dpll5_clk = clk_get(NULL, "dpll5_ck");

	clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);

	clk_prepare_enable(dpll5_clk);



	/* Program dpll5_m2_clk divider for no division */

	dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");

	clk_prepare_enable(dpll5_m2_clk);

	clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);



	clk_disable_unprepare(dpll5_m2_clk);

	clk_disable_unprepare(dpll5_clk);

}



static int __init omap3xxx_dt_clk_init(int soc_type)

{

	if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||