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Commit 052d878c authored by Jean-Baptiste Maneyrol's avatar Jean-Baptiste Maneyrol Committed by Greg Kroah-Hartman
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iio: imu: mpu6050: add missing available scan masks 



[ Upstream commit 1244a720572fd1680ac8d6b8a4235f2e8557b810 ]

Driver only supports 3-axis gyro and/or 3-axis accel.
For icm20602, temp data is mandatory for all configurations.

Fix all single and double axis configurations (almost never used) and more
importantly fix 3-axis gyro and 6-axis accel+gyro buffer on icm20602 when
temp data is not enabled.

Signed-off-by: default avatarJean-Baptiste Maneyrol <jmaneyrol@invensense.com>
Fixes: 1615fe41a195 ("iio: imu: mpu6050: Fix FIFO layout for ICM20602")
Cc: <Stable@vger.kernel.org>
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 89f3ac7e

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

+43 −0
Original line number Original line Diff line number Diff line
@@ -860,6 +860,25 @@ static const struct iio_chan_spec inv_mpu_channels[] = { 
	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),

	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),

};

};





static const unsigned long inv_mpu_scan_masks[] = {

	/* 3-axis accel */

	BIT(INV_MPU6050_SCAN_ACCL_X)

		| BIT(INV_MPU6050_SCAN_ACCL_Y)

		| BIT(INV_MPU6050_SCAN_ACCL_Z),

	/* 3-axis gyro */

	BIT(INV_MPU6050_SCAN_GYRO_X)

		| BIT(INV_MPU6050_SCAN_GYRO_Y)

		| BIT(INV_MPU6050_SCAN_GYRO_Z),

	/* 6-axis accel + gyro */

	BIT(INV_MPU6050_SCAN_ACCL_X)

		| BIT(INV_MPU6050_SCAN_ACCL_Y)

		| BIT(INV_MPU6050_SCAN_ACCL_Z)

		| BIT(INV_MPU6050_SCAN_GYRO_X)

		| BIT(INV_MPU6050_SCAN_GYRO_Y)

		| BIT(INV_MPU6050_SCAN_GYRO_Z),

	0,

};



static const struct iio_chan_spec inv_icm20602_channels[] = {

static const struct iio_chan_spec inv_icm20602_channels[] = {

	IIO_CHAN_SOFT_TIMESTAMP(INV_ICM20602_SCAN_TIMESTAMP),

	IIO_CHAN_SOFT_TIMESTAMP(INV_ICM20602_SCAN_TIMESTAMP),

	{

	{
@@ -886,6 +905,28 @@ static const struct iio_chan_spec inv_icm20602_channels[] = { 
	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_ICM20602_SCAN_ACCL_Z),

	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_ICM20602_SCAN_ACCL_Z),

};

};





static const unsigned long inv_icm20602_scan_masks[] = {

	/* 3-axis accel + temp (mandatory) */

	BIT(INV_ICM20602_SCAN_ACCL_X)

		| BIT(INV_ICM20602_SCAN_ACCL_Y)

		| BIT(INV_ICM20602_SCAN_ACCL_Z)

		| BIT(INV_ICM20602_SCAN_TEMP),

	/* 3-axis gyro + temp (mandatory) */

	BIT(INV_ICM20602_SCAN_GYRO_X)

		| BIT(INV_ICM20602_SCAN_GYRO_Y)

		| BIT(INV_ICM20602_SCAN_GYRO_Z)

		| BIT(INV_ICM20602_SCAN_TEMP),

	/* 6-axis accel + gyro + temp (mandatory) */

	BIT(INV_ICM20602_SCAN_ACCL_X)

		| BIT(INV_ICM20602_SCAN_ACCL_Y)

		| BIT(INV_ICM20602_SCAN_ACCL_Z)

		| BIT(INV_ICM20602_SCAN_GYRO_X)

		| BIT(INV_ICM20602_SCAN_GYRO_Y)

		| BIT(INV_ICM20602_SCAN_GYRO_Z)

		| BIT(INV_ICM20602_SCAN_TEMP),

	0,

};



/*

/*

 * The user can choose any frequency between INV_MPU6050_MIN_FIFO_RATE and

 * The user can choose any frequency between INV_MPU6050_MIN_FIFO_RATE and

 * INV_MPU6050_MAX_FIFO_RATE, but only these frequencies are matched by the

 * INV_MPU6050_MAX_FIFO_RATE, but only these frequencies are matched by the
@@ -1090,9 +1131,11 @@ int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, 
	if (chip_type == INV_ICM20602) {

	if (chip_type == INV_ICM20602) {

		indio_dev->channels = inv_icm20602_channels;

		indio_dev->channels = inv_icm20602_channels;

		indio_dev->num_channels = ARRAY_SIZE(inv_icm20602_channels);

		indio_dev->num_channels = ARRAY_SIZE(inv_icm20602_channels);

		indio_dev->available_scan_masks = inv_icm20602_scan_masks;

	} else {

	} else {

		indio_dev->channels = inv_mpu_channels;

		indio_dev->channels = inv_mpu_channels;

		indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);

		indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);

		indio_dev->available_scan_masks = inv_mpu_scan_masks;

	}

	}





	indio_dev->info = &mpu_info;

	indio_dev->info = &mpu_info;