Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 04421420 authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARC: timer: gfrc, rtc: build under same option (64-bit timers) 



The original distinction was done as they were developed at different
times and primarily because they are specific to UP (RTC) and SMP (GFRC).

But given that driver handles that at runtime, (i.e. not allowing
RTC as clocksource in SMP), we can simplify things a bit.

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent ec7cb87b

arch/arc/Kconfig

+2 −8
Original line number Diff line number Diff line
@@ -410,15 +410,9 @@ config ARC_HAS_DIV_REM 
	bool "Insn: div, divu, rem, remu"

	default y



config ARC_HAS_RTC

	bool "Local 64-bit r/o cycle counter"

	default n

	depends on !SMP



config ARC_HAS_GFRC

	bool "SMP synchronized 64-bit cycle counter"

config ARC_TIMERS_64BIT

	bool "64-bit r/o cycle counters RTC (up) and GFRC (smp)"

	default y

	depends on SMP



config ARC_NUMBER_OF_INTERRUPTS

	int "Number of interrupts"

arch/arc/configs/nsimosci_hs_smp_defconfig

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ CONFIG_MODULES=y 
CONFIG_ARC_PLAT_SIM=y

CONFIG_ISA_ARCV2=y

CONFIG_SMP=y

# CONFIG_ARC_HAS_GFRC is not set

# CONFIG_ARC_TIMERS_64BIT is not set

CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs_idu"

CONFIG_PREEMPT=y

# CONFIG_COMPACTION is not set

arch/arc/configs/vdk_hs38_smp_defconfig

+1 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ CONFIG_ARC_PLAT_AXS10X=y 
CONFIG_AXS103=y

CONFIG_ISA_ARCV2=y

CONFIG_SMP=y

# CONFIG_ARC_HAS_GFRC is not set

# CONFIG_ARC_TIMERS_64BIT is not set

CONFIG_ARC_UBOOT_SUPPORT=y

CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp"

CONFIG_PREEMPT=y

arch/arc/kernel/setup.c

+3 −3
Original line number Diff line number Diff line
@@ -234,11 +234,11 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) 
		       is_isa_arcompact() ? "ARCompact" : "ARCv2",

		       IS_AVAIL1(cpu->isa.be, "[Big-Endian]"));



	n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",

	n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",

		       IS_AVAIL1(cpu->extn.timer0, "Timer0 "),

		       IS_AVAIL1(cpu->extn.timer1, "Timer1 "),

		       IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ",

				 CONFIG_ARC_HAS_RTC));

		       IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT),

		       IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT));



	n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",

			   IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),

arch/arc/kernel/time.c

+1 −5
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ static int noinline arc_get_timer_clk(struct device_node *node) 


/********** Clock Source Device *********/



#ifdef CONFIG_ARC_HAS_GFRC

#ifdef CONFIG_ARC_TIMERS_64BIT



static cycle_t arc_read_gfrc(struct clocksource *cs)

{
@@ -128,10 +128,6 @@ static int __init arc_cs_setup_gfrc(struct device_node *node) 
}

CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);



#endif



#ifdef CONFIG_ARC_HAS_RTC



#define AUX_RTC_CTRL	0x103

#define AUX_RTC_LOW	0x104

#define AUX_RTC_HIGH	0x105