Loading drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c +1 −1 Original line number Diff line number Diff line Loading @@ -58,7 +58,7 @@ #define IPA_MHI_SUSPEND_SLEEP_MAX 1100 #define IPA_MHI_MAX_UL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 2 /* bit #40 in address should be asserted for MHI transfers over pcie */ #define IPA_MHI_CLIENT_HOST_ADDR_COND(addr) \ Loading drivers/platform/msm/ipa/ipa_v3/ipa_client.c +2 −1 Original line number Diff line number Diff line Loading @@ -61,7 +61,8 @@ int ipa3_enable_data_path(u32 clnt_hdl) * if DPL client is not pulling the data * on other end from IPA hw. */ if (ep->client == IPA_CLIENT_USB_DPL_CONS) if ((ep->client == IPA_CLIENT_USB_DPL_CONS) || (ep->client == IPA_CLIENT_MHI_DPL_CONS)) holb_cfg.en = IPA_HOLB_TMR_EN; else holb_cfg.en = IPA_HOLB_TMR_DIS; Loading drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c +5 −3 Original line number Diff line number Diff line Loading @@ -54,7 +54,7 @@ IPA_MHI_DBG("EXIT\n") #define IPA_MHI_MAX_UL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 2 /* bit #40 in address should be asserted for MHI transfers over pcie */ #define IPA_MHI_HOST_ADDR_COND(addr) \ Loading Loading @@ -276,8 +276,10 @@ static int ipa_mhi_start_gsi_channel(enum ipa_client_type client, ch_props.ring_base_addr = IPA_MHI_HOST_ADDR_COND( params->ch_ctx_host->rbase); if (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT || params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE) { /* Burst mode is not supported on DPL pipes */ if ((client != IPA_CLIENT_MHI_DPL_CONS) && (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT || params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE)) { burst_mode_enabled = true; } Loading drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +12 −0 Original line number Diff line number Diff line Loading @@ -1644,6 +1644,18 @@ static const struct ipa_ep_configuration ipa3_ep_mapping IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, { 16, 5, 9, 9, IPA_EE_Q6 } }, [IPA_4_0_MHI][IPA_CLIENT_USB_DPL_CONS] = { true, IPA_v4_0_MHI_GROUP_DDR, false, IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, { 15, 7, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } }, [IPA_4_0_MHI][IPA_CLIENT_MHI_DPL_CONS] = { true, IPA_v4_0_MHI_GROUP_PCIE, false, IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_PCIE, { 12, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } }, /* Only for test purpose */ [IPA_4_0_MHI][IPA_CLIENT_TEST_CONS] = { true, IPA_v4_0_GROUP_UL_DL, Loading Loading
drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c +1 −1 Original line number Diff line number Diff line Loading @@ -58,7 +58,7 @@ #define IPA_MHI_SUSPEND_SLEEP_MAX 1100 #define IPA_MHI_MAX_UL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 2 /* bit #40 in address should be asserted for MHI transfers over pcie */ #define IPA_MHI_CLIENT_HOST_ADDR_COND(addr) \ Loading
drivers/platform/msm/ipa/ipa_v3/ipa_client.c +2 −1 Original line number Diff line number Diff line Loading @@ -61,7 +61,8 @@ int ipa3_enable_data_path(u32 clnt_hdl) * if DPL client is not pulling the data * on other end from IPA hw. */ if (ep->client == IPA_CLIENT_USB_DPL_CONS) if ((ep->client == IPA_CLIENT_USB_DPL_CONS) || (ep->client == IPA_CLIENT_MHI_DPL_CONS)) holb_cfg.en = IPA_HOLB_TMR_EN; else holb_cfg.en = IPA_HOLB_TMR_DIS; Loading
drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c +5 −3 Original line number Diff line number Diff line Loading @@ -54,7 +54,7 @@ IPA_MHI_DBG("EXIT\n") #define IPA_MHI_MAX_UL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 2 /* bit #40 in address should be asserted for MHI transfers over pcie */ #define IPA_MHI_HOST_ADDR_COND(addr) \ Loading Loading @@ -276,8 +276,10 @@ static int ipa_mhi_start_gsi_channel(enum ipa_client_type client, ch_props.ring_base_addr = IPA_MHI_HOST_ADDR_COND( params->ch_ctx_host->rbase); if (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT || params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE) { /* Burst mode is not supported on DPL pipes */ if ((client != IPA_CLIENT_MHI_DPL_CONS) && (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT || params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE)) { burst_mode_enabled = true; } Loading
drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +12 −0 Original line number Diff line number Diff line Loading @@ -1644,6 +1644,18 @@ static const struct ipa_ep_configuration ipa3_ep_mapping IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, { 16, 5, 9, 9, IPA_EE_Q6 } }, [IPA_4_0_MHI][IPA_CLIENT_USB_DPL_CONS] = { true, IPA_v4_0_MHI_GROUP_DDR, false, IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, { 15, 7, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } }, [IPA_4_0_MHI][IPA_CLIENT_MHI_DPL_CONS] = { true, IPA_v4_0_MHI_GROUP_PCIE, false, IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_PCIE, { 12, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } }, /* Only for test purpose */ [IPA_4_0_MHI][IPA_CLIENT_TEST_CONS] = { true, IPA_v4_0_GROUP_UL_DL, Loading