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Commit 03ffbcdd authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "The irq department delivers:

   - Expand the generic infrastructure handling the irq migration on CPU
     hotplug and convert X86 over to it. (Thomas Gleixner)

     Aside of consolidating code this is a preparatory change for:

   - Finalizing the affinity management for multi-queue devices. The
     main change here is to shut down interrupts which are affine to a
     outgoing CPU and reenabling them when the CPU comes online again.
     That avoids moving interrupts pointlessly around and breaking and
     reestablishing affinities for no value. (Christoph Hellwig)

     Note: This contains also the BLOCK-MQ and NVME changes which depend
     on the rework of the irq core infrastructure. Jens acked them and
     agreed that they should go with the irq changes.

   - Consolidation of irq domain code (Marc Zyngier)

   - State tracking consolidation in the core code (Jeffy Chen)

   - Add debug infrastructure for hierarchical irq domains (Thomas
     Gleixner)

   - Infrastructure enhancement for managing generic interrupt chips via
     devmem (Bartosz Golaszewski)

   - Constification work all over the place (Tobias Klauser)

   - Two new interrupt controller drivers for MVEBU (Thomas Petazzoni)

   - The usual set of fixes, updates and enhancements all over the
     place"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (112 commits)
  irqchip/or1k-pic: Fix interrupt acknowledgement
  irqchip/irq-mvebu-gicp: Allocate enough memory for spi_bitmap
  irqchip/gic-v3: Fix out-of-bound access in gic_set_affinity
  nvme: Allocate queues for all possible CPUs
  blk-mq: Create hctx for each present CPU
  blk-mq: Include all present CPUs in the default queue mapping
  genirq: Avoid unnecessary low level irq function calls
  genirq: Set irq masked state when initializing irq_desc
  genirq/timings: Add infrastructure for estimating the next interrupt arrival time
  genirq/timings: Add infrastructure to track the interrupt timings
  genirq/debugfs: Remove pointless NULL pointer check
  irqchip/gic-v3-its: Don't assume GICv3 hardware supports 16bit INTID
  irqchip/gic-v3-its: Add ACPI NUMA node mapping
  irqchip/gic-v3-its-platform-msi: Make of_device_ids const
  irqchip/gic-v3-its: Make of_device_ids const
  irqchip/irq-mvebu-icu: Add new driver for Marvell ICU
  irqchip/irq-mvebu-gicp: Add new driver for Marvell GICP
  dt-bindings/interrupt-controller: Add DT binding for the Marvell ICU
  genirq/irqdomain: Remove auto-recursive hierarchy support
  irqchip/MSI: Use irq_domain_update_bus_token instead of an open coded access
  ...
parents 1b044f1c f9632de4

Documentation/IRQ-domain.txt

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Original line number Diff line number Diff line
@@ -231,5 +231,42 @@ needs to: 
4) No need to implement irq_domain_ops.map and irq_domain_ops.unmap,

   they are unused with hierarchy irq_domain.



Hierarchy irq_domain may also be used to support other architectures,

such as ARM, ARM64 etc.
 
Hierarchy irq_domain is in no way x86 specific, and is heavily used to

support other architectures, such as ARM, ARM64 etc.



=== Debugging ===



If you switch on CONFIG_IRQ_DOMAIN_DEBUG (which depends on

CONFIG_IRQ_DOMAIN and CONFIG_DEBUG_FS), you will find a new file in

your debugfs mount point, called irq_domain_mapping. This file

contains a live snapshot of all the IRQ domains in the system:



 name              mapped  linear-max  direct-max  devtree-node

 pl061                  8           8           0  /smb/gpio@e0080000

 pl061                  8           8           0  /smb/gpio@e1050000

 pMSI                   0           0           0  /interrupt-controller@e1101000/v2m@e0080000

 MSI                   37           0           0  /interrupt-controller@e1101000/v2m@e0080000

 GICv2m                37           0           0  /interrupt-controller@e1101000/v2m@e0080000

 GICv2                448         448           0  /interrupt-controller@e1101000



it also iterates over the interrupts to display their mapping in the

domains, and makes the domain stacking visible:





irq    hwirq    chip name        chip data           active  type            domain

    1  0x00019  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2

    2  0x0001d  GICv2            0xffff00000916bfd8          LINEAR          GICv2

    3  0x0001e  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2

    4  0x0001b  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2

    5  0x0001a  GICv2            0xffff00000916bfd8          LINEAR          GICv2

[...]

   96  0x81808  MSI              0x          (null)           RADIX          MSI

   96+ 0x00063  GICv2m           0xffff8003ee116980           RADIX          GICv2m

   96+ 0x00063  GICv2            0xffff00000916bfd8          LINEAR          GICv2

   97  0x08800  MSI              0x          (null)     *     RADIX          MSI

   97+ 0x00064  GICv2m           0xffff8003ee116980     *     RADIX          GICv2m

   97+ 0x00064  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2



Here, interrupts 1-5 are only using a single domain, while 96 and 97

are build out of a stack of three domain, each level performing a

particular function.

Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt

+5 −2
Original line number Diff line number Diff line
@@ -3,8 +3,11 @@ Allwinner Sunxi NMI Controller 


Required properties:



- compatible : should be "allwinner,sun7i-a20-sc-nmi" or

  "allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi"

- compatible : should be one of the following:

  - "allwinner,sun7i-a20-sc-nmi"

  - "allwinner,sun6i-a31-sc-nmi" (deprecated)

  - "allwinner,sun6i-a31-r-intc"

  - "allwinner,sun9i-a80-nmi"

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt

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+25 −0
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Device tree configuration for the I2C Interrupt Controller on the AST24XX and

AST25XX SoCs.



Required Properties:

- #address-cells	: should be 1

- #size-cells 		: should be 1

- #interrupt-cells 	: should be 1

- compatible 		: should be "aspeed,ast2400-i2c-ic"

			  or "aspeed,ast2500-i2c-ic"

- reg			: address start and range of controller

- interrupts		: interrupt number

- interrupt-controller	: denotes that the controller receives and fires

			  new interrupts for child busses



Example:



i2c_ic: interrupt-controller@0 {

	#address-cells = <1>;

	#size-cells = <1>;

	#interrupt-cells = <1>;

	compatible = "aspeed,ast2400-i2c-ic";

	reg = <0x0 0x40>;

	interrupts = <12>;

	interrupt-controller;

};

Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt

+5 −4
Original line number Diff line number Diff line 
Aspeed Vectored Interrupt Controller



These bindings are for the Aspeed AST2400 interrupt controller register layout.

The SoC has an legacy register layout, but this driver does not support that

mode of operation.

These bindings are for the Aspeed interrupt controller. The AST2400 and

AST2500 SoC families include a legacy register layout before a re-designed

layout, but the bindings do not prescribe the use of one or the other.



Required properties:



- compatible : should be "aspeed,ast2400-vic".

- compatible : "aspeed,ast2400-vic"

               "aspeed,ast2500-vic"



- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt

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+27 −0
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Marvell GICP Controller

-----------------------



GICP is a Marvell extension of the GIC that allows to trigger GIC SPI

interrupts by doing a memory transaction. It is used by the ICU

located in the Marvell CP110 to turn wired interrupts inside the CP

into GIC SPI interrupts.



Required properties:



- compatible: Must be "marvell,ap806-gicp"



- reg: Must be the address and size of the GICP SPI registers



- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available

  for this GICP



- msi-controller: indicates that this is an MSI controller



Example:



gicp_spi: gicp-spi@3f0040 {

	compatible = "marvell,ap806-gicp";

	reg = <0x3f0040 0x10>;

	marvell,spi-ranges = <64 64>, <288 64>;

	msi-controller;

};