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Commit 03af2045 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Use the cached min/min/rpe values in the vlv debugfs code 



No need to re-read the hardware rps fuses when we already have all the
values tucked away in dev_priv->rps.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDeepak S <deepak.s@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ca2aed6c

drivers/gpu/drm/i915/i915_debugfs.c

+10 −9
Original line number Original line Diff line number Diff line
@@ -1108,20 +1108,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		seq_printf(m, "Max overclocked frequency: %dMHz\n",

		seq_printf(m, "Max overclocked frequency: %dMHz\n",

			   dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);

			   dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);

	} else if (IS_VALLEYVIEW(dev)) {

	} else if (IS_VALLEYVIEW(dev)) {

		u32 freq_sts, val;

		u32 freq_sts;





		mutex_lock(&dev_priv->rps.hw_lock);

		mutex_lock(&dev_priv->rps.hw_lock);

		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);

		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);

		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);

		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);





		val = valleyview_rps_max_freq(dev_priv);

		seq_printf(m, "max GPU freq: %d MHz\n",

		seq_printf(m, "max GPU freq: %d MHz\n",

			   vlv_gpu_freq(dev_priv, val));

			   dev_priv->rps.max_freq);





		val = valleyview_rps_min_freq(dev_priv);

		seq_printf(m, "min GPU freq: %d MHz\n",

		seq_printf(m, "min GPU freq: %d MHz\n",

			   vlv_gpu_freq(dev_priv, val));

			   dev_priv->rps.min_freq);



		seq_printf(m, "efficient (RPe) frequency: %d MHz\n",

			   dev_priv->rps.efficient_freq);





		seq_printf(m, "current GPU freq: %d MHz\n",

		seq_printf(m, "current GPU freq: %d MHz\n",

			   vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));

			   vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
@@ -3632,8 +3633,8 @@ i915_max_freq_set(void *data, u64 val) 
	if (IS_VALLEYVIEW(dev)) {

	if (IS_VALLEYVIEW(dev)) {

		val = vlv_freq_opcode(dev_priv, val);

		val = vlv_freq_opcode(dev_priv, val);





		hw_max = valleyview_rps_max_freq(dev_priv);

		hw_max = dev_priv->rps.max_freq;

		hw_min = valleyview_rps_min_freq(dev_priv);

		hw_min = dev_priv->rps.min_freq;

	} else {

	} else {

		do_div(val, GT_FREQUENCY_MULTIPLIER);

		do_div(val, GT_FREQUENCY_MULTIPLIER);
@@ -3713,8 +3714,8 @@ i915_min_freq_set(void *data, u64 val) 
	if (IS_VALLEYVIEW(dev)) {

	if (IS_VALLEYVIEW(dev)) {

		val = vlv_freq_opcode(dev_priv, val);

		val = vlv_freq_opcode(dev_priv, val);





		hw_max = valleyview_rps_max_freq(dev_priv);

		hw_max = dev_priv->rps.max_freq;

		hw_min = valleyview_rps_min_freq(dev_priv);

		hw_min = dev_priv->rps.min_freq;

	} else {

	} else {

		do_div(val, GT_FREQUENCY_MULTIPLIER);

		do_div(val, GT_FREQUENCY_MULTIPLIER);

drivers/gpu/drm/i915/i915_drv.h

+0 −2
Original line number Original line Diff line number Diff line
@@ -2684,8 +2684,6 @@ extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 
extern void intel_init_pch_refclk(struct drm_device *dev);

extern void intel_init_pch_refclk(struct drm_device *dev);

extern void gen6_set_rps(struct drm_device *dev, u8 val);

extern void gen6_set_rps(struct drm_device *dev, u8 val);

extern void valleyview_set_rps(struct drm_device *dev, u8 val);

extern void valleyview_set_rps(struct drm_device *dev, u8 val);

extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);

extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);

extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,

extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,

				  bool enable);

				  bool enable);

extern void intel_detect_pch(struct drm_device *dev);

extern void intel_detect_pch(struct drm_device *dev);

drivers/gpu/drm/i915/intel_pm.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -3781,7 +3781,7 @@ void gen6_update_ring_freq(struct drm_device *dev) 
	mutex_unlock(&dev_priv->rps.hw_lock);

	mutex_unlock(&dev_priv->rps.hw_lock);

}

}





int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)

static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)

{

{

	u32 val, rp0;

	u32 val, rp0;
@@ -3801,7 +3801,7 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) 
	return rpe;

	return rpe;

}

}





int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)

static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)

{

{

	u32 val, rpn;

	u32 val, rpn;
@@ -3810,7 +3810,7 @@ int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) 
	return rpn;

	return rpn;

}

}





int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)

static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)

{

{

	u32 val, rp0;

	u32 val, rp0;
@@ -3835,7 +3835,7 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) 
	return rpe;

	return rpe;

}

}





int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)

static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)

{

{

	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;

	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;

}

}