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Commit 035724b6 authored by Pranav Patel's avatar Pranav Patel
Browse files

msm: kgsl: Add support for A702 GPU 



Initial change to support A702. A702 is A6XX family
derivative hence does not require extensive changes.

Change-Id: Ia211c3d5a363669d9ffa870818d7a7ec15e5fe45
Signed-off-by: default avatarPranav Patel <pranavp@codeaurora.org>
parent d35ab61c

drivers/gpu/msm/a6xx_reg.h

+10 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _A6XX_REG_H
@@ -527,6 +527,15 @@ 
#define A6XX_RBBM_CLOCK_MODE_HLSQ	 0x0011b

#define A6XX_RBBM_CLOCK_DELAY_HLSQ       0x0011c

#define A6XX_RBBM_CLOCK_HYST_HLSQ        0x0011d

#define A6XX_RBBM_CLOCK_CNTL_FCHE        0x00123

#define A6XX_RBBM_CLOCK_DELAY_FCHE       0x00124

#define A6XX_RBBM_CLOCK_HYST_FCHE        0x00125

#define A6XX_RBBM_CLOCK_CNTL_GLC         0x0012B

#define A6XX_RBBM_CLOCK_DELAY_GLC        0x00129

#define A6XX_RBBM_CLOCK_HYST_GLC         0x0012A

#define A6XX_RBBM_CLOCK_CNTL_MHUB        0x00126

#define A6XX_RBBM_CLOCK_DELAY_MHUB       0x00127

#define A6XX_RBBM_CLOCK_HYST_MHUB        0x00128



/* DBGC_CFG registers */

#define A6XX_DBGC_CFG_DBGBUS_SEL_A                  0x600

drivers/gpu/msm/adreno-gpulist.h

+81 −1
Original line number Diff line number Diff line
@@ -1117,7 +1117,7 @@ static const struct adreno_reglist a640_hwcg_regs[] = { 
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},

};



/* These apply to a640, a680, a612 and a610 */

/* These apply to a640, a680, a612, a610 and a702 */

static const struct adreno_reglist a640_vbif_regs[] = {

	{A6XX_GBIF_QSB_SIDE0, 0x00071620},

	{A6XX_GBIF_QSB_SIDE1, 0x00071620},
@@ -1409,6 +1409,85 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = { 
	.protected_regs = a630_protected_regs,

};



static const struct adreno_reglist a702_hwcg_regs[] = {

	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},

	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},

	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},

	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},

	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},

	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},

	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},

	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},

	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},

	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},

	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},

	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},

	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},

	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},

	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},

	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A6XX_RBBM_ISDB_CNT, 0x00000182},

	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},

	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},

	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},

	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},

	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},

	{A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222},

	{A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000},

	{A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222},

	{A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000},

	{A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002},

	{A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000},

};



static const struct adreno_a6xx_core adreno_gpu_core_a702 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A702, 7, 0, 2, ANY_ID),

		.features = ADRENO_64BIT | ADRENO_CONTENT_PROTECTION |

			ADRENO_APRIV,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_size = (SZ_128K + SZ_4K),

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x00080000,

	.sqefw_name = "a702_sqe.fw",

	.zap_name = "a702_zap",

	.hwcg = a702_hwcg_regs,

	.hwcg_count = ARRAY_SIZE(a702_hwcg_regs),

	.vbif = a640_vbif_regs,

	.vbif_count = ARRAY_SIZE(a640_vbif_regs),

	.hang_detect_cycles = 0x3ffff,

	.protected_regs = a620_protected_regs,

};



static const struct adreno_gpu_core *adreno_gpulist[] = {

	&adreno_gpu_core_a306.base,

	&adreno_gpu_core_a306a.base,
@@ -1440,4 +1519,5 @@ static const struct adreno_gpu_core *adreno_gpulist[] = { 
	&adreno_gpu_core_a612.base,

	&adreno_gpu_core_a616.base,

	&adreno_gpu_core_a610.base,

	&adreno_gpu_core_a702.base,

};

drivers/gpu/msm/adreno.h

+5 −2
Original line number Diff line number Diff line
@@ -206,6 +206,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A640 = 640,

	ADRENO_REV_A650 = 650,

	ADRENO_REV_A680 = 680,

	ADRENO_REV_A702 = 702,

};



#define ADRENO_SOFT_FAULT BIT(0)
@@ -1161,8 +1162,9 @@ static inline int adreno_is_a505_or_a506(struct adreno_device *adreno_dev) 


static inline int adreno_is_a6xx(struct adreno_device *adreno_dev)

{

	return ADRENO_GPUREV(adreno_dev) >= 600 &&

			ADRENO_GPUREV(adreno_dev) < 700;

	int rev = ADRENO_GPUREV(adreno_dev);



	return (rev >= 600 && rev < 700) || (rev == 702);

}



ADRENO_TARGET(a610, ADRENO_REV_A610)
@@ -1174,6 +1176,7 @@ ADRENO_TARGET(a630, ADRENO_REV_A630) 
ADRENO_TARGET(a640, ADRENO_REV_A640)

ADRENO_TARGET(a650, ADRENO_REV_A650)

ADRENO_TARGET(a680, ADRENO_REV_A680)

ADRENO_TARGET(a702, ADRENO_REV_A702)



/*

 * All the derived chipsets from A615 needs to be added to this

drivers/gpu/msm/adreno_a6xx.c

+11 −5
Original line number Diff line number Diff line
@@ -226,7 +226,8 @@ __get_rbbm_clock_cntl_on(struct adreno_device *adreno_dev) 
{

	if (adreno_is_a630(adreno_dev))

		return 0x8AA8AA02;

	else if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev))

	else if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev) ||

		adreno_is_a702(adreno_dev))

		return 0xAAA8AA82;

	else

		return 0x8AA8AA82;
@@ -310,7 +311,7 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) 
	 */



	if (gmu_core_isenabled(device) && !adreno_is_a612(adreno_dev) &&

		!adreno_is_a610(adreno_dev))

		!adreno_is_a610(adreno_dev) && !(adreno_is_a702(adreno_dev)))

		gmu_core_regrmw(device,

			A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
@@ -324,7 +325,7 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) 
	 * Hence skip GMU_GX registers for A612.

	 */

	if (gmu_core_isenabled(device) && !adreno_is_a612(adreno_dev) &&

		!adreno_is_a610(adreno_dev))

		!adreno_is_a610(adreno_dev) && !adreno_is_a702(adreno_dev))

		gmu_core_regrmw(device,

			A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
@@ -459,10 +460,12 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
	kgsl_regwrite(device, A6XX_UCHE_CACHE_WAYS, 0x4);



	/* ROQ sizes are twice as big on a640/a680 than on a630 */

	if (ADRENO_GPUREV(adreno_dev) >= ADRENO_REV_A640) {

	if (ADRENO_GPUREV(adreno_dev) >= ADRENO_REV_A640 &&

		ADRENO_GPUREV(adreno_dev) <= ADRENO_REV_A680) {

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);

	} else if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) {

	} else if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev) ||

			adreno_is_a702(adreno_dev)) {

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060);

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16);

	} else {
@@ -474,6 +477,9 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
		/* For A612 and A610 Mem pool size is reduced to 48 */

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_SIZE, 48);

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_DBG_ADDR, 47);

	} else if (adreno_is_a702(adreno_dev)) {

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_SIZE, 64);

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_DBG_ADDR, 63);

	} else {

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_SIZE, 128);

	}