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Commit 033b1142 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6 

Conflicts:
	net/bluetooth/l2cap_core.c
parents f5caadbb e6625fa4

Documentation/filesystems/nilfs2.txt

+0 −1
Original line number Diff line number Diff line
@@ -40,7 +40,6 @@ Features which NILFS2 does not support yet: 
	- POSIX ACLs

	- quotas

	- fsck

	- resize

	- defragmentation



Mount options

arch/arm/mach-davinci/board-dm365-evm.c

+2 −2
Original line number Diff line number Diff line
@@ -520,7 +520,7 @@ static void __init evm_init_cpld(void) 
	 */

	if (have_imager()) {

		label = "HD imager";

		mux |= 1;

		mux |= 2;



		/* externally mux MMC1/ENET/AIC33 to imager */

		mux |= BIT(6) | BIT(5) | BIT(3);
@@ -540,7 +540,7 @@ static void __init evm_init_cpld(void) 
		resets &= ~BIT(1);



		if (have_tvp7002()) {

			mux |= 2;

			mux |= 1;

			resets &= ~BIT(2);

			label = "tvp7002 HD";

		} else {

arch/arm/mach-davinci/gpio.c

+16 −5
Original line number Diff line number Diff line
@@ -254,8 +254,10 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) 
{

	struct davinci_gpio_regs __iomem *g;

	u32 mask = 0xffff;

	struct davinci_gpio_controller *d;



	g = (__force struct davinci_gpio_regs __iomem *) irq_desc_get_handler_data(desc);

	d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);

	g = (struct davinci_gpio_regs __iomem *)d->regs;



	/* we only care about one bank */

	if (irq & 1)
@@ -274,11 +276,14 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) 
		if (!status)

			break;

		__raw_writel(status, &g->intstat);

		if (irq & 1)

			status >>= 16;



		/* now demux them to the right lowlevel handler */

		n = (int)irq_get_handler_data(irq);

		n = d->irq_base;

		if (irq & 1) {

			n += 16;

			status >>= 16;

		}



		while (status) {

			res = ffs(status);

			n += res;
@@ -424,7 +429,13 @@ static int __init davinci_gpio_irq_setup(void) 


		/* set up all irqs in this bank */

		irq_set_chained_handler(bank_irq, gpio_irq_handler);

		irq_set_handler_data(bank_irq, (__force void *)g);



		/*

		 * Each chip handles 32 gpios, and each irq bank consists of 16

		 * gpio irqs. Pass the irq bank's corresponding controller to

		 * the chained irq handler.

		 */

		irq_set_handler_data(bank_irq, &chips[gpio / 32]);



		for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {

			irq_set_chip(irq, &gpio_irqchip);

arch/arm/mach-davinci/irq.c

+6 −0
Original line number Diff line number Diff line
@@ -52,6 +52,12 @@ davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) 
	struct irq_chip_type *ct;



	gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);

	if (!gc) {

		pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",

		       __func__, irq_start);

		return;

	}



	ct = gc->chip_types;

	ct->chip.irq_ack = irq_gc_ack_set_bit;

	ct->chip.irq_mask = irq_gc_mask_clr_bit;

arch/arm/mach-ixp4xx/common.c

+8 −2
Original line number Diff line number Diff line
@@ -419,14 +419,20 @@ static void notrace ixp4xx_update_sched_clock(void) 
/*

 * clocksource

 */



static cycle_t ixp4xx_clocksource_read(struct clocksource *c)

{

	return *IXP4XX_OSTS;

}



unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;

EXPORT_SYMBOL(ixp4xx_timer_freq);

static void __init ixp4xx_clocksource_init(void)

{

	init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq);



	clocksource_mmio_init(&IXP4XX_OSTS, "OSTS", ixp4xx_timer_freq, 200, 32,

			clocksource_mmio_readl_up);

	clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,

			ixp4xx_clocksource_read);

}



/*