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Commit 02f0aaaa authored by Laurent Pinchart's avatar Laurent Pinchart
Browse files

drm: rcar-du: lvds: Fix LVDS clock frequency range 



According to the latest versions of both the Gen2 and Gen3 datasheets,
the operating range for the LVDS clock is 31 MHz to 148.5 MHz on all
SoCs. Update the driver accordingly.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
parent 3e5907a1

drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c

+2 −8
Original line number Original line Diff line number Diff line
@@ -201,17 +201,11 @@ int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, struct drm_crtc *crtc, 
void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds,

void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds,

				  struct drm_display_mode *mode)

				  struct drm_display_mode *mode)

{

{

	struct rcar_du_device *rcdu = lvds->dev;



	/*

	/*

	 * The internal LVDS encoder has a restricted clock frequency operating

	 * The internal LVDS encoder has a restricted clock frequency operating

	 * range (30MHz to 150MHz on Gen2, 25.175MHz to 148.5MHz on Gen3). Clamp

	 * range (31MHz to 148.5MHz). Clamp the clock accordingly.

	 * the clock accordingly.

	 */

	 */

	if (rcdu->info->gen < 3)

	mode->clock = clamp(mode->clock, 31000, 148500);

		mode->clock = clamp(mode->clock, 30000, 150000);

	else

		mode->clock = clamp(mode->clock, 25175, 148500);

}

}





void rcar_du_lvdsenc_set_mode(struct rcar_du_lvdsenc *lvds,

void rcar_du_lvdsenc_set_mode(struct rcar_du_lvdsenc *lvds,