Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 02c5c032 authored by Bard Liao's avatar Bard Liao Committed by Mark Brown
Browse files

ASoC: rt5645: set sel_i2s_pre_div1 to 2 

The i2s clock pre-divider 1 is used for both i2s1 and sysclk.
The i2s1 is usually used for the main i2s and the pre-divider
will be set in hw_params function.

However, if i2s2 is used, the pre-divider is not set in the hw_params
function and the default value of i2s clock pre-divider 1 is too high
for sysclk and DMIC usage. Fix by overriding default divider value to 2.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=95681


Tested-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: default avatarBard Liao <bardliao@realtek.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent a5de5b74

sound/soc/codecs/rt5645.c

+3 −0
Original line number Diff line number Diff line
@@ -3833,6 +3833,9 @@ static int rt5645_i2c_probe(struct i2c_client *i2c, 
		}

	}



	regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1,

		RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2);



	if (rt5645->pdata.jd_invert) {

		regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,

			RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);