Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 02a72bd8 authored by Sunil Goutham's avatar Sunil Goutham Committed by David S. Miller
Browse files

net: thunderx: Enable CQE_RX desc's extension fields 



Unlike 88xx, CQE_RX descriptor's tunnelling extension i.e CQE_RX2_S
is always enabled on 81xx/83xx and HW does insert these fields into
CQE_RX. As a result receive buffer addresses will now be present at
7th word of CQE_RX instead of 6th.

Enable CQE_RX2_S on 88xx pass 2.x as well.

Signed-off-by: default avatarSunil Goutham <sgoutham@cavium.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3a397ebe

drivers/net/ethernet/cavium/thunder/nic.h

+8 −1
Original line number Diff line number Diff line
@@ -493,7 +493,14 @@ static inline int nic_get_node_id(struct pci_dev *pdev) 


static inline bool pass1_silicon(struct pci_dev *pdev)

{

	return pdev->revision < 8;

	return (pdev->revision < 8) &&

		(pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF);

}



static inline bool pass2_silicon(struct pci_dev *pdev)

{

	return (pdev->revision >= 8) &&

		(pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF);

}



int nicvf_set_real_num_queues(struct net_device *netdev,

drivers/net/ethernet/cavium/thunder/nic_main.c

+7 −0
Original line number Diff line number Diff line
@@ -799,6 +799,13 @@ static void nic_handle_mbx_intr(struct nicpf *nic, int vf) 
			   (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |

			   (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);

		nic_reg_write(nic, reg_addr, mbx.rq.cfg);

		/* Enable CQE_RX2_S extension in CQE_RX descriptor.

		 * This gets appended by default on 81xx/83xx chips,

		 * for consistency enabling the same on 88xx pass2

		 * where this is introduced.

		 */

		if (pass2_silicon(nic->pdev))

			nic_reg_write(nic, NIC_PF_RX_CFG, 0x01);

		break;

	case NIC_MBOX_MSG_RQ_BP_CFG:

		reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG |

drivers/net/ethernet/cavium/thunder/nic_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
#define   NIC_PF_MAILBOX_ENA_W1C		(0x0450)

#define   NIC_PF_MAILBOX_ENA_W1S		(0x0470)

#define   NIC_PF_RX_ETYPE_0_7			(0x0500)

#define   NIC_PF_RX_CFG				(0x05D0)

#define   NIC_PF_PKIND_0_15_CFG			(0x0600)

#define   NIC_PF_ECC0_FLIP0			(0x1000)

#define   NIC_PF_ECC1_FLIP0			(0x1008)

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

+11 −1
Original line number Diff line number Diff line
@@ -1190,7 +1190,17 @@ struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic, struct cqe_rx_t *cqe_rx) 
	u64 *rb_ptrs = NULL;



	rb_lens = (void *)cqe_rx + (3 * sizeof(u64));

	/* Except 88xx pass1 on all other chips CQE_RX2_S is added to

	 * CQE_RX at word6, hence buffer pointers move by word

	 *

	 * Use existing 'hw_tso' flag which will be set for all chips

	 * except 88xx pass1 instead of a additional cache line

	 * access (or miss) by using pci dev's revision.

	 */

	if (!nic->hw_tso)

		rb_ptrs = (void *)cqe_rx + (6 * sizeof(u64));

	else

		rb_ptrs = (void *)cqe_rx + (7 * sizeof(u64));



	netdev_dbg(nic->netdev, "%s rb_cnt %d rb0_ptr %llx rb0_sz %d\n",

		   __func__, cqe_rx->rb_cnt, cqe_rx->rb0_ptr, cqe_rx->rb0_sz);