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Commit 0243f7ba authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter
Browse files

drm/i915: group link_standby setup and let this info visible everywhere. 



No functional changes on this patch. Just grouping the link_standy decision
to avoid miss any change. Also making this info available everywhere
which will help to decide when to use vbt's tp time on following patch.

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarDurgadoss R <durgadoss.r@intel.com>
[danvet: Slight editing of the commit message which was one huge
run-on sentence.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 8522b716

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -789,6 +789,7 @@ struct i915_psr { 
	bool active;

	struct delayed_work work;

	unsigned busy_frontbuffer_bits;

	bool link_standby;

};



enum intel_pch {

drivers/gpu/drm/i915/intel_psr.c

+9 −10
Original line number Diff line number Diff line
@@ -143,7 +143,6 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t aux_clock_divider;

	int precharge = 0x3;

	bool only_standby = dev_priv->vbt.psr.full_link;

	static const uint8_t aux_msg[] = {

		[0] = DP_AUX_NATIVE_WRITE << 4,

		[1] = DP_SET_POWER >> 8,
@@ -157,11 +156,8 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) 


	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);



	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)

		only_standby = true;



	/* Enable PSR in sink */

	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)

	if (dev_priv->psr.link_standby)

		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,

				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);

	else
@@ -226,12 +222,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) 
			       dev_priv->vbt.psr.idle_frames + 1 : 2;

	uint32_t val = 0x0;

	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;

	bool only_standby = dev_priv->vbt.psr.full_link;



	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)

		only_standby = true;



	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {

	if (dev_priv->psr.link_standby) {

		val |= EDP_PSR_LINK_STANDBY;

		val |= EDP_PSR_TP2_TP3_TIME_0us;

		val |= EDP_PSR_TP1_TIME_0us;
@@ -341,6 +333,13 @@ void intel_psr_enable(struct intel_dp *intel_dp) 
	if (!intel_psr_match_conditions(intel_dp))

		goto unlock;



	/* First we check VBT, but we must respect sink and source

	 * known restrictions */

	dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;

	if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) ||

	    (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A))

		dev_priv->psr.link_standby = true;



	dev_priv->psr.busy_frontbuffer_bits = 0;



	if (HAS_DDI(dev)) {